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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/traps.h
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*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_TRAP_H
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#define __ASM_TRAP_H
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#include <linux/list.h>
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#include <asm/esr.h>
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#include <asm/sections.h>
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struct pt_regs;
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struct undef_hook {
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struct list_head node;
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u32 instr_mask;
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u32 instr_val;
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u64 pstate_mask;
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u64 pstate_val;
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int (*fn)(struct pt_regs *regs, u32 instr);
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};
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void register_undef_hook(struct undef_hook *hook);
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void unregister_undef_hook(struct undef_hook *hook);
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void force_signal_inject(int signal, int code, unsigned long address);
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void arm64_notify_segfault(unsigned long addr);
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void arm64_force_sig_fault(int signo, int code, void __user *addr, const char *str);
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void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, const char *str);
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void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr, const char *str);
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/*
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* Move regs->pc to next instruction and do necessary setup before it
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* is executed.
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*/
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void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
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static inline int __in_irqentry_text(unsigned long ptr)
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{
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return ptr >= (unsigned long)&__irqentry_text_start &&
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ptr < (unsigned long)&__irqentry_text_end;
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}
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static inline int in_exception_text(unsigned long ptr)
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{
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int in;
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in = ptr >= (unsigned long)&__exception_text_start &&
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ptr < (unsigned long)&__exception_text_end;
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return in ? : __in_irqentry_text(ptr);
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}
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static inline int in_entry_text(unsigned long ptr)
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{
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return ptr >= (unsigned long)&__entry_text_start &&
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ptr < (unsigned long)&__entry_text_end;
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}
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/*
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* CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
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* to indicate whether this ESR has a RAS encoding. CPUs without this feature
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* have a ISS-Valid bit in the same position.
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* If this bit is set, we know its not a RAS SError.
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* If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
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* errors share the same encoding as an all-zeros encoding from a CPU that
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* doesn't support RAS.
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*/
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static inline bool arm64_is_ras_serror(u32 esr)
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{
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WARN_ON(preemptible());
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if (esr & ESR_ELx_IDS)
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return false;
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if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
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return true;
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else
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return false;
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}
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/*
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* Return the AET bits from a RAS SError's ESR.
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*
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* It is implementation defined whether Uncategorized errors are containable.
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* We treat them as Uncontainable.
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* Non-RAS SError's are reported as Uncontained/Uncategorized.
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*/
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static inline u32 arm64_ras_serror_get_severity(u32 esr)
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{
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u32 aet = esr & ESR_ELx_AET;
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if (!arm64_is_ras_serror(esr)) {
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/* Not a RAS error, we can't interpret the ESR. */
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return ESR_ELx_AET_UC;
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}
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/*
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* AET is RES0 if 'the value returned in the DFSC field is not
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* [ESR_ELx_FSC_SERROR]'
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*/
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if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
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/* No severity information : Uncategorized */
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return ESR_ELx_AET_UC;
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}
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return aet;
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}
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bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr);
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void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr);
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#endif
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