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08224a7d41
Add omap2_clk_enable_autoidle_all to am43xx_init_late otherwise the call to omap2_clk_disable_autoidle_all in am43xx_init_early may cause some clocks to always stay active and prevent low power mode transitions. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
804 lines
18 KiB
C
804 lines
18 KiB
C
/*
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* linux/arch/arm/mach-omap2/io.c
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*
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* OMAP2 I/O mapping code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Copyright (C) 2007-2009 Texas Instruments
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*
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* Author:
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* Juha Yrjola <juha.yrjola@nokia.com>
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* Syed Khasim <x0khasim@ti.com>
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*
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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#include <linux/omap-dma.h>
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#include "omap_hwmod.h"
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#include "soc.h"
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#include "iomap.h"
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#include "voltage.h"
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "common.h"
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#include "clock.h"
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#include "clock2xxx.h"
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#include "clock3xxx.h"
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#include "omap-pm.h"
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#include "sdrc.h"
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#include "control.h"
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#include "serial.h"
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#include "sram.h"
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#include "cm2xxx.h"
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#include "cm3xxx.h"
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#include "cm33xx.h"
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#include "cm44xx.h"
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#include "prm.h"
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#include "cm.h"
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#include "prcm_mpu44xx.h"
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#include "prminst44xx.h"
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#include "prm2xxx.h"
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#include "prm3xxx.h"
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#include "prm33xx.h"
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#include "prm44xx.h"
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#include "opp2xxx.h"
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/*
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* omap_clk_soc_init: points to a function that does the SoC-specific
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* clock initializations
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*/
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static int (*omap_clk_soc_init)(void);
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
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static struct map_desc omap24xx_io_desc[] __initdata = {
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{
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.virtual = L3_24XX_VIRT,
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.pfn = __phys_to_pfn(L3_24XX_PHYS),
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.length = L3_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_24XX_VIRT,
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.pfn = __phys_to_pfn(L4_24XX_PHYS),
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.length = L4_24XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#ifdef CONFIG_SOC_OMAP2420
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static struct map_desc omap242x_io_desc[] __initdata = {
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{
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.virtual = DSP_MEM_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
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.length = DSP_MEM_2420_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_IPI_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
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.length = DSP_IPI_2420_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_MMU_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
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.length = DSP_MMU_2420_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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static struct map_desc omap243x_io_desc[] __initdata = {
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{
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.virtual = L4_WK_243X_VIRT,
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.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
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.length = L4_WK_243X_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
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.length = OMAP243X_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
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.length = OMAP243X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
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.length = OMAP243X_SMS_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct map_desc omap34xx_io_desc[] __initdata = {
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{
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.virtual = L3_34XX_VIRT,
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.pfn = __phys_to_pfn(L3_34XX_PHYS),
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.length = L3_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP34XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
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.length = OMAP34XX_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
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.length = OMAP343X_SMS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
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.length = OMAP343X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_PER_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
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.length = L4_PER_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_EMU_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
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.length = L4_EMU_34XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#ifdef CONFIG_SOC_TI81XX
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static struct map_desc omapti81xx_io_desc[] __initdata = {
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
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static struct map_desc omapam33xx_io_desc[] __initdata = {
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_WK_AM33XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
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.length = L4_WK_AM33XX_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static struct map_desc omap44xx_io_desc[] __initdata = {
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{
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.virtual = L3_44XX_VIRT,
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.pfn = __phys_to_pfn(L3_44XX_PHYS),
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.length = L3_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_44XX_PHYS),
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.length = L4_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
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.length = L4_PER_44XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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#ifdef CONFIG_SOC_OMAP5
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static struct map_desc omap54xx_io_desc[] __initdata = {
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{
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.virtual = L3_54XX_VIRT,
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.pfn = __phys_to_pfn(L3_54XX_PHYS),
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.length = L3_54XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_54XX_VIRT,
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.pfn = __phys_to_pfn(L4_54XX_PHYS),
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.length = L4_54XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_WK_54XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
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.length = L4_WK_54XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER_54XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
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.length = L4_PER_54XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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#ifdef CONFIG_SOC_DRA7XX
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static struct map_desc dra7xx_io_desc[] __initdata = {
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{
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.virtual = L4_CFG_MPU_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
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.length = L4_CFG_MPU_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L3_MAIN_SN_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
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.length = L3_MAIN_SN_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER1_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
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.length = L4_PER1_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER2_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
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.length = L4_PER2_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER3_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
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.length = L4_PER3_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_CFG_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
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.length = L4_CFG_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_WKUP_DRA7XX_VIRT,
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.pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
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.length = L4_WKUP_DRA7XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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#ifdef CONFIG_SOC_OMAP2420
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void __init omap242x_map_io(void)
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{
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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void __init omap243x_map_io(void)
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{
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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void __init omap3_map_io(void)
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{
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iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
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}
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#endif
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#ifdef CONFIG_SOC_TI81XX
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void __init ti81xx_map_io(void)
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{
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iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
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}
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#endif
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#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
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void __init am33xx_map_io(void)
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{
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iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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void __init omap4_map_io(void)
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{
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iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
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omap_barriers_init();
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}
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#endif
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#ifdef CONFIG_SOC_OMAP5
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void __init omap5_map_io(void)
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{
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iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
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omap_barriers_init();
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}
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#endif
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#ifdef CONFIG_SOC_DRA7XX
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void __init dra7xx_map_io(void)
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{
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iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
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}
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#endif
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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* Sets the CORE DPLL3 M2 divider to the same value that it's at
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* currently. This has the effect of setting the SDRC SDRAM AC timing
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* registers to the values currently defined by the kernel. Currently
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* only defined for OMAP3; will return 0 if called on OMAP2. Returns
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* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
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* or passes along the return value of clk_set_rate().
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*/
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static int __init _omap2_init_reprogram_sdrc(void)
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{
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struct clk *dpll3_m2_ck;
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int v = -EINVAL;
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long rate;
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if (!cpu_is_omap34xx())
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return 0;
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dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
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if (IS_ERR(dpll3_m2_ck))
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return -EINVAL;
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rate = clk_get_rate(dpll3_m2_ck);
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pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
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v = clk_set_rate(dpll3_m2_ck, rate);
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if (v)
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pr_err("dpll3_m2_clk rate change failed: %d\n", v);
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clk_put(dpll3_m2_ck);
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return v;
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}
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static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
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{
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return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
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}
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static void __init omap_hwmod_init_postsetup(void)
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{
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u8 postsetup_state;
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/* Set the default postsetup state for all hwmods */
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#ifdef CONFIG_PM
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postsetup_state = _HWMOD_STATE_IDLE;
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#else
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postsetup_state = _HWMOD_STATE_ENABLED;
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#endif
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omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
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omap_pm_if_early_init();
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}
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static void __init __maybe_unused omap_common_late_init(void)
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{
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omap_mux_late_init();
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omap2_common_pm_late_init();
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omap_soc_device_init();
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}
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#ifdef CONFIG_SOC_OMAP2420
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void __init omap2420_init_early(void)
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{
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omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
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omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
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OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
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omap2_control_base_init();
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omap2xxx_check_revision();
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omap2_prcm_base_init();
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omap2xxx_voltagedomains_init();
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omap242x_powerdomains_init();
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omap242x_clockdomains_init();
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omap2420_hwmod_init();
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omap_hwmod_init_postsetup();
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omap_clk_soc_init = omap2420_dt_clk_init;
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rate_table = omap2420_rate_table;
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}
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void __init omap2420_init_late(void)
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{
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omap_common_late_init();
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omap2_pm_init();
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omap2_clk_enable_autoidle_all();
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}
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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void __init omap2430_init_early(void)
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{
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omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
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omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
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OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
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omap2_control_base_init();
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omap2xxx_check_revision();
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omap2_prcm_base_init();
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omap2xxx_voltagedomains_init();
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omap243x_powerdomains_init();
|
|
omap243x_clockdomains_init();
|
|
omap2430_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_clk_soc_init = omap2430_dt_clk_init;
|
|
rate_table = omap2430_rate_table;
|
|
}
|
|
|
|
void __init omap2430_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap2_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Currently only board-omap3beagle.c should call this because of the
|
|
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
|
|
*/
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap3_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
|
|
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
|
|
OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
|
|
/* XXX: remove these once OMAP3 is DT only */
|
|
if (!of_have_populated_dt()) {
|
|
omap2_set_globals_control(
|
|
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
|
|
NULL);
|
|
}
|
|
omap2_control_base_init();
|
|
omap3xxx_check_revision();
|
|
omap3xxx_check_features();
|
|
omap2_prcm_base_init();
|
|
/* XXX: remove these once OMAP3 is DT only */
|
|
if (!of_have_populated_dt()) {
|
|
omap3xxx_prm_init(NULL);
|
|
omap3xxx_cm_init(NULL);
|
|
}
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
if (!of_have_populated_dt()) {
|
|
omap3_control_legacy_iomap_init();
|
|
if (soc_is_am35xx())
|
|
omap_clk_soc_init = am35xx_clk_legacy_init;
|
|
else if (cpu_is_omap3630())
|
|
omap_clk_soc_init = omap36xx_clk_legacy_init;
|
|
else if (omap_rev() == OMAP3430_REV_ES1_0)
|
|
omap_clk_soc_init = omap3430es1_clk_legacy_init;
|
|
else
|
|
omap_clk_soc_init = omap3430_clk_legacy_init;
|
|
}
|
|
}
|
|
|
|
void __init omap3430_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = omap3430_dt_clk_init;
|
|
}
|
|
|
|
void __init omap35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = omap3430_dt_clk_init;
|
|
}
|
|
|
|
void __init omap3630_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = omap3630_dt_clk_init;
|
|
}
|
|
|
|
void __init am35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = am35xx_dt_clk_init;
|
|
}
|
|
|
|
void __init omap3_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap3_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
|
|
void __init omap3430_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap3_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
|
|
void __init omap35xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap3_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
|
|
void __init omap3630_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap3_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
|
|
void __init am35xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap3_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
|
|
void __init ti81xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_TI81XX
|
|
void __init ti814x_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(TI814X_CLASS,
|
|
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
|
omap2_control_base_init();
|
|
omap3xxx_check_revision();
|
|
ti81xx_check_features();
|
|
omap2_prcm_base_init();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
ti814x_clockdomains_init();
|
|
dm814x_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = dm814x_dt_clk_init;
|
|
}
|
|
|
|
void __init ti816x_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(TI816X_CLASS,
|
|
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
|
omap2_control_base_init();
|
|
omap3xxx_check_revision();
|
|
ti81xx_check_features();
|
|
omap2_prcm_base_init();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
ti816x_clockdomains_init();
|
|
dm816x_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
if (of_have_populated_dt())
|
|
omap_clk_soc_init = dm816x_dt_clk_init;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
void __init am33xx_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(AM335X_CLASS,
|
|
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
|
|
omap2_control_base_init();
|
|
omap3xxx_check_revision();
|
|
am33xx_check_features();
|
|
omap2_prcm_base_init();
|
|
am33xx_powerdomains_init();
|
|
am33xx_clockdomains_init();
|
|
am33xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_clk_soc_init = am33xx_dt_clk_init;
|
|
}
|
|
|
|
void __init am33xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM43XX
|
|
void __init am43xx_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(AM335X_CLASS,
|
|
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
|
|
omap2_control_base_init();
|
|
omap3xxx_check_revision();
|
|
am33xx_check_features();
|
|
omap2_prcm_base_init();
|
|
am43xx_powerdomains_init();
|
|
am43xx_clockdomains_init();
|
|
am43xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_l2_cache_init();
|
|
omap_clk_soc_init = am43xx_dt_clk_init;
|
|
}
|
|
|
|
void __init am43xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap4430_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(OMAP443X_CLASS,
|
|
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
|
|
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
|
|
omap2_control_base_init();
|
|
omap4xxx_check_revision();
|
|
omap4xxx_check_features();
|
|
omap2_prcm_base_init();
|
|
omap4_pm_init_early();
|
|
omap44xx_voltagedomains_init();
|
|
omap44xx_powerdomains_init();
|
|
omap44xx_clockdomains_init();
|
|
omap44xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_l2_cache_init();
|
|
omap_clk_soc_init = omap4xxx_dt_clk_init;
|
|
}
|
|
|
|
void __init omap4430_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap4_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
void __init omap5_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(OMAP54XX_CLASS,
|
|
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
|
|
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
|
|
omap2_control_base_init();
|
|
omap4_pm_init_early();
|
|
omap2_prcm_base_init();
|
|
omap5xxx_check_revision();
|
|
omap54xx_voltagedomains_init();
|
|
omap54xx_powerdomains_init();
|
|
omap54xx_clockdomains_init();
|
|
omap54xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_clk_soc_init = omap5xxx_dt_clk_init;
|
|
}
|
|
|
|
void __init omap5_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap4_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_DRA7XX
|
|
void __init dra7xx_init_early(void)
|
|
{
|
|
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
|
|
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
|
|
omap2_control_base_init();
|
|
omap4_pm_init_early();
|
|
omap2_prcm_base_init();
|
|
dra7xxx_check_revision();
|
|
dra7xx_powerdomains_init();
|
|
dra7xx_clockdomains_init();
|
|
dra7xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap_clk_soc_init = dra7xx_dt_clk_init;
|
|
}
|
|
|
|
void __init dra7xx_init_late(void)
|
|
{
|
|
omap_common_late_init();
|
|
omap4_pm_init();
|
|
omap2_clk_enable_autoidle_all();
|
|
}
|
|
#endif
|
|
|
|
|
|
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
|
struct omap_sdrc_params *sdrc_cs1)
|
|
{
|
|
omap_sram_init();
|
|
|
|
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
|
_omap2_init_reprogram_sdrc();
|
|
}
|
|
}
|
|
|
|
int __init omap_clk_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!omap_clk_soc_init)
|
|
return 0;
|
|
|
|
ti_clk_init_features();
|
|
|
|
omap2_clk_setup_ll_ops();
|
|
|
|
if (of_have_populated_dt()) {
|
|
ret = omap_control_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = omap_prcm_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
of_clk_init(NULL);
|
|
|
|
ti_dt_clk_init_retry_clks();
|
|
|
|
ti_dt_clockdomains_setup();
|
|
}
|
|
|
|
ret = omap_clk_soc_init();
|
|
|
|
return ret;
|
|
}
|