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8be99c7b8b
The RTC reference and MSSPLL were previously not documented or defined,
as they were unused. Add their defines to the PolarFire SoC header.
Fixes: 2145bb687e ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-6-conor.dooley@microchip.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
49 lines
1.0 KiB
C
49 lines
1.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Daire McNamara,<daire.mcnamara@microchip.com>
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* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
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#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
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#define CLK_CPU 0
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#define CLK_AXI 1
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#define CLK_AHB 2
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#define CLK_ENVM 3
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#define CLK_MAC0 4
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#define CLK_MAC1 5
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#define CLK_MMC 6
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#define CLK_TIMER 7
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#define CLK_MMUART0 8
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#define CLK_MMUART1 9
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#define CLK_MMUART2 10
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#define CLK_MMUART3 11
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#define CLK_MMUART4 12
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#define CLK_SPI0 13
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#define CLK_SPI1 14
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#define CLK_I2C0 15
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#define CLK_I2C1 16
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#define CLK_CAN0 17
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#define CLK_CAN1 18
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#define CLK_USB 19
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#define CLK_RESERVED 20
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#define CLK_RTC 21
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#define CLK_QSPI 22
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#define CLK_GPIO0 23
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#define CLK_GPIO1 24
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#define CLK_GPIO2 25
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#define CLK_DDRC 26
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#define CLK_FIC0 27
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#define CLK_FIC1 28
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#define CLK_FIC2 29
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#define CLK_FIC3 30
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#define CLK_ATHENA 31
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#define CLK_CFM 32
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#define CLK_RTCREF 33
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#define CLK_MSSPLL 34
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#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
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