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320da785db
Commit a5a10afe04
("reset: meson: add level reset support for GX SoC
family") only enabled the level resets for the newer GX SoC family.
However, the older 32-Meson SoCs (Meson8, Meson8b and Meson8m2) also
support level resets using the same offset as the newer GX SoCs.
This removes the separation between Meson8b and the GX SoCs from the
reset-meson driver to enable the level resets also on Meson8b.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
174 lines
5.4 KiB
C
174 lines
5.4 KiB
C
/*
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* Amlogic Meson Reset Controller driver
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/of_device.h>
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#define REG_COUNT 8
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#define BITS_PER_REG 32
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#define LEVEL_OFFSET 0x7c
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struct meson_reset {
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void __iomem *reg_base;
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struct reset_controller_dev rcdev;
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spinlock_t lock;
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};
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static int meson_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct meson_reset *data =
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container_of(rcdev, struct meson_reset, rcdev);
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unsigned int bank = id / BITS_PER_REG;
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr = data->reg_base + (bank << 2);
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writel(BIT(offset), reg_addr);
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return 0;
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}
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static int meson_reset_level(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct meson_reset *data =
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container_of(rcdev, struct meson_reset, rcdev);
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unsigned int bank = id / BITS_PER_REG;
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(reg_addr);
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if (assert)
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writel(reg & ~BIT(offset), reg_addr);
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else
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writel(reg | BIT(offset), reg_addr);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int meson_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return meson_reset_level(rcdev, id, true);
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}
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static int meson_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return meson_reset_level(rcdev, id, false);
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}
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static const struct reset_control_ops meson_reset_ops = {
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.reset = meson_reset_reset,
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.assert = meson_reset_assert,
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.deassert = meson_reset_deassert,
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};
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static const struct of_device_id meson_reset_dt_ids[] = {
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{ .compatible = "amlogic,meson8b-reset" },
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{ .compatible = "amlogic,meson-gxbb-reset" },
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{ .compatible = "amlogic,meson-axg-reset" },
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{ /* sentinel */ },
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};
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static int meson_reset_probe(struct platform_device *pdev)
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{
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struct meson_reset *data;
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struct resource *res;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->reg_base))
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return PTR_ERR(data->reg_base);
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platform_set_drvdata(pdev, data);
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
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data->rcdev.ops = &meson_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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}
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static struct platform_driver meson_reset_driver = {
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.probe = meson_reset_probe,
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.driver = {
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.name = "meson_reset",
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.of_match_table = meson_reset_dt_ids,
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},
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};
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builtin_platform_driver(meson_reset_driver);
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