mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-13 22:14:20 +08:00
75ce0cdb62
MT8173 MMPLL frequency settings are different from common PLLs. It needs different post divider settings for some ranges of frequency. This patch add support for MT8173 MMPLL frequency setting by adding div-rate table to lookup suitable post divider setting under a specified frequency. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
||
|---|---|---|
| .. | ||
| clk-gate.c | ||
| clk-gate.h | ||
| clk-mt8135.c | ||
| clk-mt8173.c | ||
| clk-mtk.c | ||
| clk-mtk.h | ||
| clk-pll.c | ||
| Makefile | ||
| reset.c | ||