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81f56e5375
Features currently supported: - 39-bit address space for user and kernel (each) - 4KB and 64KB page configurations - Compat (32-bit) user applications (ARMv7, EABI only) - Flattened Device Tree (mandated for all AArch64 platforms) - ARM generic timers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJQabRiAAoJEGvWsS0AyF7xXgcQAK+FTXt0ikdQYMkV5AIZXb9i xHRhuiZWx2vKyk0mCqpyGLY58GSmSb6uTBg/2P2Ej7vXdH/RB2goPzjlspfjkDL4 o8RJp7eQ07Uz3KRDYEJgMP8xKZid6KFG93RJ6TjjpKZLuDBdwiG1GP1vb0jVcWfo ttZrj/aI8lMcqrh3Vq5qefP7GWP1OVATqeaGTiT7oo38pXwF3t237xfBr2iDGFBp ZgIRddrxpa7JYUesfJDDDdGHvLq7Vh2jJV+io9qasBZDrtppGJIhZ0vUni2DgIi7 r4i1LcynDN4JaG0maZ4U/YQm74TCD4BqxV8GJ7zwLPTWeN+of+skjhPSLOkA+0fp I+sWjXlv200gDfJZ9qnUld2kFpoDfJi2b7fNDouSDd2OhmVOVWG3jnVP4Z7meVSb O8BYzWDdsAiabuwciUY3OsmW6424lT93b2v86Vncs4unKMvEjOPxYZbUxhqX8f2j gsmWwwD/yS4THx2B6OyW9VT3I5J6miqs2Glt/GG6vPWT5AKQJn9jCxKaBGhPMPIs xe5/GycBYjdk/Y8qRjegxFbEqzQuiRzmkeFn5jwjmBLqpGNbZDpvMaL6adhAKM5/ v6UIKa91ra4fC9N0h6G61pOc9N9DbT8wPbCbdYY0RMTMRuLDZDgAM3Bvz0r2APdD 96leNy6vx684hbkCSLJs =buJB -----END PGP SIGNATURE----- Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull arm64 support from Catalin Marinas: "Linux support for the 64-bit ARM architecture (AArch64) Features currently supported: - 39-bit address space for user and kernel (each) - 4KB and 64KB page configurations - Compat (32-bit) user applications (ARMv7, EABI only) - Flattened Device Tree (mandated for all AArch64 platforms) - ARM generic timers" * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (35 commits) arm64: ptrace: remove obsolete ptrace request numbers from user headers arm64: Do not set the SMP/nAMP processor bit arm64: MAINTAINERS update arm64: Build infrastructure arm64: Miscellaneous header files arm64: Generic timers support arm64: Loadable modules arm64: Miscellaneous library functions arm64: Performance counters support arm64: Add support for /proc/sys/debug/exception-trace arm64: Debugging support arm64: Floating point and SIMD arm64: 32-bit (compat) applications support arm64: User access library functions arm64: Signal handling support arm64: VDSO support arm64: System calls handling arm64: ELF definitions arm64: SMP support arm64: DMA mapping API ...
249 lines
5.6 KiB
C
249 lines
5.6 KiB
C
#ifndef _PERF_PERF_H
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#define _PERF_PERF_H
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struct winsize;
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void get_term_dimensions(struct winsize *ws);
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#if defined(__i386__)
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#include "../../arch/x86/include/asm/unistd.h"
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 336
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#endif
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#endif
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#if defined(__x86_64__)
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#include "../../arch/x86/include/asm/unistd.h"
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#define rmb() asm volatile("lfence" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 298
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#endif
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#endif
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#ifdef __powerpc__
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#include "../../arch/powerpc/include/asm/unistd.h"
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#define rmb() asm volatile ("sync" ::: "memory")
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#define cpu_relax() asm volatile ("" ::: "memory");
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __s390__
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#include "../../arch/s390/include/asm/unistd.h"
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#define rmb() asm volatile("bcr 15,0" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory");
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#endif
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#ifdef __sh__
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#include "../../arch/sh/include/asm/unistd.h"
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#if defined(__SH4A__) || defined(__SH5__)
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# define rmb() asm volatile("synco" ::: "memory")
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#else
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# define rmb() asm volatile("" ::: "memory")
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#endif
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu type"
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#endif
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#ifdef __hppa__
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#include "../../arch/parisc/include/asm/unistd.h"
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#define rmb() asm volatile("" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory");
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __sparc__
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#include "../../arch/sparc/include/asm/unistd.h"
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#define rmb() asm volatile("":::"memory")
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#define cpu_relax() asm volatile("":::"memory")
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __alpha__
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#include "../../arch/alpha/include/asm/unistd.h"
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#define rmb() asm volatile("mb" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu model"
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#endif
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#ifdef __ia64__
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#include "../../arch/ia64/include/asm/unistd.h"
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#define rmb() asm volatile ("mf" ::: "memory")
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#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
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#define CPUINFO_PROC "model name"
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#endif
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#ifdef __arm__
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#include "../../arch/arm/include/asm/unistd.h"
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/*
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* Use the __kuser_memory_barrier helper in the CPU helper page. See
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* arch/arm/kernel/entry-armv.S in the kernel source for details.
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*/
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#define rmb() ((void(*)(void))0xffff0fa0)()
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#define cpu_relax() asm volatile("":::"memory")
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#define CPUINFO_PROC "Processor"
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#endif
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#ifdef __aarch64__
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#include "../../arch/arm64/include/asm/unistd.h"
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#define rmb() asm volatile("dmb ld" ::: "memory")
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#define cpu_relax() asm volatile("yield" ::: "memory")
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#endif
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#ifdef __mips__
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#include "../../arch/mips/include/asm/unistd.h"
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#define rmb() asm volatile( \
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".set mips2\n\t" \
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"sync\n\t" \
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".set mips0" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu model"
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#endif
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#include <time.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/syscall.h>
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#include "../../include/linux/perf_event.h"
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#include "util/types.h"
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#include <stdbool.h>
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struct perf_mmap {
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void *base;
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int mask;
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unsigned int prev;
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};
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static inline unsigned int perf_mmap__read_head(struct perf_mmap *mm)
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{
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struct perf_event_mmap_page *pc = mm->base;
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int head = pc->data_head;
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rmb();
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return head;
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}
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static inline void perf_mmap__write_tail(struct perf_mmap *md,
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unsigned long tail)
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{
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struct perf_event_mmap_page *pc = md->base;
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/*
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* ensure all reads are done before we write the tail out.
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*/
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/* mb(); */
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pc->data_tail = tail;
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}
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/*
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* prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
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* counters in the current task.
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*/
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#define PR_TASK_PERF_EVENTS_DISABLE 31
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#define PR_TASK_PERF_EVENTS_ENABLE 32
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#ifndef NSEC_PER_SEC
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# define NSEC_PER_SEC 1000000000ULL
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#endif
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static inline unsigned long long rdclock(void)
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{
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struct timespec ts;
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clock_gettime(CLOCK_MONOTONIC, &ts);
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return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
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}
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/*
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* Pick up some kernel type conventions:
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*/
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#define __user
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#define asmlinkage
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#define unlikely(x) __builtin_expect(!!(x), 0)
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#define min(x, y) ({ \
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typeof(x) _min1 = (x); \
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typeof(y) _min2 = (y); \
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(void) (&_min1 == &_min2); \
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_min1 < _min2 ? _min1 : _min2; })
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static inline int
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sys_perf_event_open(struct perf_event_attr *attr,
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pid_t pid, int cpu, int group_fd,
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unsigned long flags)
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{
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return syscall(__NR_perf_event_open, attr, pid, cpu,
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group_fd, flags);
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}
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#define MAX_COUNTERS 256
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#define MAX_NR_CPUS 256
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struct ip_callchain {
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u64 nr;
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u64 ips[0];
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};
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struct branch_flags {
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u64 mispred:1;
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u64 predicted:1;
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u64 reserved:62;
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};
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struct branch_entry {
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u64 from;
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u64 to;
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struct branch_flags flags;
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};
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struct branch_stack {
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u64 nr;
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struct branch_entry entries[0];
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};
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extern bool perf_host, perf_guest;
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extern const char perf_version_string[];
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void pthread__unblock_sigwinch(void);
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#include "util/target.h"
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enum perf_call_graph_mode {
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CALLCHAIN_NONE,
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CALLCHAIN_FP,
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CALLCHAIN_DWARF
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};
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struct perf_record_opts {
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struct perf_target target;
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int call_graph;
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bool group;
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bool inherit_stat;
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bool no_delay;
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bool no_inherit;
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bool no_samples;
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bool pipe_output;
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bool raw_samples;
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bool sample_address;
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bool sample_time;
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bool sample_id_all_missing;
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bool exclude_guest_missing;
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bool period;
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unsigned int freq;
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unsigned int mmap_pages;
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unsigned int user_freq;
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u64 branch_stack;
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u64 default_interval;
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u64 user_interval;
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u16 stack_dump_size;
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};
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#endif
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