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402bfb3c13
The A80 SoC has configuration registers for I/O bias voltage. Incorrect settings would make the affected peripherals inoperable in some cases, such as Ethernet RGMII signals biased at 2.5V with the settings still at 3.3V. However low speed signals such as MDIO on the same group of pins seem to be unaffected. Previously there was no way to know what the actual voltage used was, short of hard-coding a value in the device tree. With the new pin bank regulator supply support in place, the driver can now query the regulator for its voltage, and if it's valid (as opposed to being the dummy regulator), set the bias voltage setting accordingly. Add a quirk to denote the presence of the configuration registers, and a function to set the correct setting based on the voltage read back from the regulator. This is only done when the regulator is first acquired and enabled. While it would be nice to have a notifier on the regulator so that when the voltage changes, the driver can update the setting, in practice no board currently supports dynamic changing of the I/O voltages. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1547 lines
37 KiB
C
1547 lines
37 KiB
C
/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/of_clk.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/regulator/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include "../core.h"
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#include "pinctrl-sunxi.h"
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static struct irq_chip sunxi_pinctrl_edge_irq_chip;
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static struct irq_chip sunxi_pinctrl_level_irq_chip;
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static struct sunxi_pinctrl_group *
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sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
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{
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int i;
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for (i = 0; i < pctl->ngroups; i++) {
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struct sunxi_pinctrl_group *grp = pctl->groups + i;
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if (!strcmp(grp->name, group))
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return grp;
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}
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return NULL;
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}
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static struct sunxi_pinctrl_function *
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sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *name)
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{
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struct sunxi_pinctrl_function *func = pctl->functions;
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int i;
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for (i = 0; i < pctl->nfunctions; i++) {
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if (!func[i].name)
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break;
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if (!strcmp(func[i].name, name))
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return func + i;
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *pin_name,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (!strcmp(pin->pin.name, pin_name)) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name) &&
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(!func->variant ||
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func->variant & pctl->variant))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
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const u16 pin_num,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (pin->pin.number == pin_num) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->ngroups;
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}
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static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->groups[group].name;
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}
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static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*pins = (unsigned *)&pctl->groups[group].pin;
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*num_pins = 1;
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return 0;
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}
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static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
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{
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return of_find_property(node, "bias-pull-up", NULL) ||
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of_find_property(node, "bias-pull-down", NULL) ||
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of_find_property(node, "bias-disable", NULL) ||
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of_find_property(node, "allwinner,pull", NULL);
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}
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static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
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{
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return of_find_property(node, "drive-strength", NULL) ||
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of_find_property(node, "allwinner,drive", NULL);
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}
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static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
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{
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u32 val;
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/* Try the new style binding */
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if (of_find_property(node, "bias-pull-up", NULL))
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return PIN_CONFIG_BIAS_PULL_UP;
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if (of_find_property(node, "bias-pull-down", NULL))
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return PIN_CONFIG_BIAS_PULL_DOWN;
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if (of_find_property(node, "bias-disable", NULL))
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return PIN_CONFIG_BIAS_DISABLE;
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/* And fall back to the old binding */
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if (of_property_read_u32(node, "allwinner,pull", &val))
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return -EINVAL;
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switch (val) {
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case SUN4I_PINCTRL_NO_PULL:
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return PIN_CONFIG_BIAS_DISABLE;
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case SUN4I_PINCTRL_PULL_UP:
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return PIN_CONFIG_BIAS_PULL_UP;
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case SUN4I_PINCTRL_PULL_DOWN:
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return PIN_CONFIG_BIAS_PULL_DOWN;
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}
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return -EINVAL;
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}
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static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
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{
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u32 val;
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/* Try the new style binding */
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if (!of_property_read_u32(node, "drive-strength", &val)) {
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/* We can't go below 10mA ... */
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if (val < 10)
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return -EINVAL;
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/* ... and only up to 40 mA ... */
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if (val > 40)
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val = 40;
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/* by steps of 10 mA */
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return rounddown(val, 10);
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}
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/* And then fall back to the old binding */
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if (of_property_read_u32(node, "allwinner,drive", &val))
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return -EINVAL;
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return (val + 1) * 10;
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}
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static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
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{
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const char *function;
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int ret;
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/* Try the generic binding */
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ret = of_property_read_string(node, "function", &function);
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if (!ret)
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return function;
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/* And fall back to our legacy one */
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ret = of_property_read_string(node, "allwinner,function", &function);
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if (!ret)
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return function;
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return NULL;
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}
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static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
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int *npins)
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{
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int count;
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/* Try the generic binding */
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count = of_property_count_strings(node, "pins");
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if (count > 0) {
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*npins = count;
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return "pins";
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}
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/* And fall back to our legacy one */
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count = of_property_count_strings(node, "allwinner,pins");
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if (count > 0) {
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*npins = count;
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return "allwinner,pins";
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}
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return NULL;
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}
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static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
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unsigned int *len)
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{
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unsigned long *pinconfig;
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unsigned int configlen = 0, idx = 0;
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int ret;
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if (sunxi_pctrl_has_drive_prop(node))
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configlen++;
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if (sunxi_pctrl_has_bias_prop(node))
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configlen++;
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/*
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* If we don't have any configuration, bail out
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*/
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if (!configlen)
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return NULL;
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pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
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if (!pinconfig)
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return ERR_PTR(-ENOMEM);
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if (sunxi_pctrl_has_drive_prop(node)) {
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int drive = sunxi_pctrl_parse_drive_prop(node);
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if (drive < 0) {
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ret = drive;
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goto err_free;
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}
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pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
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drive);
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}
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if (sunxi_pctrl_has_bias_prop(node)) {
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int pull = sunxi_pctrl_parse_bias_prop(node);
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int arg = 0;
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if (pull < 0) {
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ret = pull;
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goto err_free;
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}
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if (pull != PIN_CONFIG_BIAS_DISABLE)
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arg = 1; /* hardware uses weak pull resistors */
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pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
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}
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*len = configlen;
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return pinconfig;
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err_free:
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kfree(pinconfig);
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return ERR_PTR(ret);
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}
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static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *node,
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struct pinctrl_map **map,
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unsigned *num_maps)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long *pinconfig;
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struct property *prop;
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const char *function, *pin_prop;
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const char *group;
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int ret, npins, nmaps, configlen = 0, i = 0;
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*map = NULL;
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*num_maps = 0;
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function = sunxi_pctrl_parse_function_prop(node);
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if (!function) {
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dev_err(pctl->dev, "missing function property in node %pOFn\n",
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node);
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return -EINVAL;
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}
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pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
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if (!pin_prop) {
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dev_err(pctl->dev, "missing pins property in node %pOFn\n",
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node);
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return -EINVAL;
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}
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/*
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* We have two maps for each pin: one for the function, one
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* for the configuration (bias, strength, etc).
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*
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* We might be slightly overshooting, since we might not have
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* any configuration.
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*/
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nmaps = npins * 2;
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*map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
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if (IS_ERR(pinconfig)) {
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ret = PTR_ERR(pinconfig);
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goto err_free_map;
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}
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of_property_for_each_string(node, pin_prop, prop, group) {
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struct sunxi_pinctrl_group *grp =
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sunxi_pinctrl_find_group_by_name(pctl, group);
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if (!grp) {
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dev_err(pctl->dev, "unknown pin %s", group);
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continue;
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}
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if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
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grp->name,
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function)) {
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dev_err(pctl->dev, "unsupported function %s on pin %s",
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function, group);
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continue;
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}
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(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[i].data.mux.group = group;
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(*map)[i].data.mux.function = function;
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i++;
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if (pinconfig) {
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(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
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(*map)[i].data.configs.group_or_pin = group;
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(*map)[i].data.configs.configs = pinconfig;
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(*map)[i].data.configs.num_configs = configlen;
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i++;
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}
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}
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*num_maps = i;
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/*
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* We know have the number of maps we need, we can resize our
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* map array
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*/
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*map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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return 0;
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err_free_map:
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kfree(*map);
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*map = NULL;
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return ret;
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}
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static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map,
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unsigned num_maps)
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{
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int i;
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/* pin config is never in the first map */
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for (i = 1; i < num_maps; i++) {
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if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
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continue;
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/*
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* All the maps share the same pin config,
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* free only the first one we find.
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*/
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kfree(map[i].data.configs.configs);
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break;
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}
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kfree(map);
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}
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static const struct pinctrl_ops sunxi_pctrl_ops = {
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.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
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.dt_free_map = sunxi_pctrl_dt_free_map,
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.get_groups_count = sunxi_pctrl_get_groups_count,
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.get_group_name = sunxi_pctrl_get_group_name,
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.get_group_pins = sunxi_pctrl_get_group_pins,
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};
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static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
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u32 *offset, u32 *shift, u32 *mask)
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{
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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*offset = sunxi_dlevel_reg(pin);
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*shift = sunxi_dlevel_offset(pin);
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*mask = DLEVEL_PINS_MASK;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_DISABLE:
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*offset = sunxi_pull_reg(pin);
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*shift = sunxi_pull_offset(pin);
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*mask = PULL_PINS_MASK;
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
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unsigned long *config)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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u32 offset, shift, mask, val;
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u16 arg;
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int ret;
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pin -= pctl->desc->pin_base;
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ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
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if (ret < 0)
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return ret;
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val = (readl(pctl->membase + offset) >> shift) & mask;
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switch (pinconf_to_config_param(*config)) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = (val + 1) * 10;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (val != SUN4I_PINCTRL_PULL_UP)
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return -EINVAL;
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arg = 1; /* hardware is weak pull-up */
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (val != SUN4I_PINCTRL_PULL_DOWN)
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return -EINVAL;
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arg = 1; /* hardware is weak pull-down */
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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if (val != SUN4I_PINCTRL_NO_PULL)
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return -EINVAL;
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arg = 0;
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break;
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default:
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/* sunxi_pconf_reg should catch anything unsupported */
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WARN_ON(1);
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return -ENOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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return 0;
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}
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|
|
static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
|
|
unsigned group,
|
|
unsigned long *config)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_pinctrl_group *g = &pctl->groups[group];
|
|
|
|
/* We only support 1 pin per group. Chain it to the pin callback */
|
|
return sunxi_pconf_get(pctldev, g->pin, config);
|
|
}
|
|
|
|
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
|
|
unsigned group,
|
|
unsigned long *configs,
|
|
unsigned num_configs)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_pinctrl_group *g = &pctl->groups[group];
|
|
unsigned pin = g->pin - pctl->desc->pin_base;
|
|
int i;
|
|
|
|
for (i = 0; i < num_configs; i++) {
|
|
enum pin_config_param param;
|
|
unsigned long flags;
|
|
u32 offset, shift, mask, reg;
|
|
u32 arg, val;
|
|
int ret;
|
|
|
|
param = pinconf_to_config_param(configs[i]);
|
|
arg = pinconf_to_config_argument(configs[i]);
|
|
|
|
ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
switch (param) {
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
if (arg < 10 || arg > 40)
|
|
return -EINVAL;
|
|
/*
|
|
* We convert from mA to what the register expects:
|
|
* 0: 10mA
|
|
* 1: 20mA
|
|
* 2: 30mA
|
|
* 3: 40mA
|
|
*/
|
|
val = arg / 10 - 1;
|
|
break;
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
val = 0;
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
if (arg == 0)
|
|
return -EINVAL;
|
|
val = 1;
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
if (arg == 0)
|
|
return -EINVAL;
|
|
val = 2;
|
|
break;
|
|
default:
|
|
/* sunxi_pconf_reg should catch anything unsupported */
|
|
WARN_ON(1);
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
reg = readl(pctl->membase + offset);
|
|
reg &= ~(mask << shift);
|
|
writel(reg | val << shift, pctl->membase + offset);
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
} /* for each config */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinconf_ops sunxi_pconf_ops = {
|
|
.is_generic = true,
|
|
.pin_config_get = sunxi_pconf_get,
|
|
.pin_config_group_get = sunxi_pconf_group_get,
|
|
.pin_config_group_set = sunxi_pconf_group_set,
|
|
};
|
|
|
|
static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
|
|
unsigned pin,
|
|
struct regulator *supply)
|
|
{
|
|
u32 val, reg;
|
|
int uV;
|
|
|
|
if (!pctl->desc->has_io_bias_cfg)
|
|
return 0;
|
|
|
|
uV = regulator_get_voltage(supply);
|
|
if (uV < 0)
|
|
return uV;
|
|
|
|
/* Might be dummy regulator with no voltage set */
|
|
if (uV == 0)
|
|
return 0;
|
|
|
|
/* Configured value must be equal or greater to actual voltage */
|
|
if (uV <= 1800000)
|
|
val = 0x0; /* 1.8V */
|
|
else if (uV <= 2500000)
|
|
val = 0x6; /* 2.5V */
|
|
else if (uV <= 2800000)
|
|
val = 0x9; /* 2.8V */
|
|
else if (uV <= 3000000)
|
|
val = 0xA; /* 3.0V */
|
|
else
|
|
val = 0xD; /* 3.3V */
|
|
|
|
pin -= pctl->desc->pin_base;
|
|
|
|
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
|
|
reg &= ~IO_BIAS_MASK;
|
|
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->nfunctions;
|
|
}
|
|
|
|
static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
|
|
unsigned function)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->functions[function].name;
|
|
}
|
|
|
|
static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
|
|
unsigned function,
|
|
const char * const **groups,
|
|
unsigned * const num_groups)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*groups = pctl->functions[function].groups;
|
|
*num_groups = pctl->functions[function].ngroups;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
|
|
unsigned pin,
|
|
u8 config)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned long flags;
|
|
u32 val, mask;
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
pin -= pctl->desc->pin_base;
|
|
val = readl(pctl->membase + sunxi_mux_reg(pin));
|
|
mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
|
|
writel((val & ~mask) | config << sunxi_mux_offset(pin),
|
|
pctl->membase + sunxi_mux_reg(pin));
|
|
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
|
|
unsigned function,
|
|
unsigned group)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_pinctrl_group *g = pctl->groups + group;
|
|
struct sunxi_pinctrl_function *func = pctl->functions + function;
|
|
struct sunxi_desc_function *desc =
|
|
sunxi_pinctrl_desc_find_function_by_name(pctl,
|
|
g->name,
|
|
func->name);
|
|
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
sunxi_pmx_set(pctldev, g->pin, desc->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned offset,
|
|
bool input)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_desc_function *desc;
|
|
const char *func;
|
|
|
|
if (input)
|
|
func = "gpio_in";
|
|
else
|
|
func = "gpio_out";
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
sunxi_pmx_set(pctldev, offset, desc->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned short bank = offset / PINS_PER_BANK;
|
|
unsigned short bank_offset = bank - pctl->desc->pin_base /
|
|
PINS_PER_BANK;
|
|
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
|
|
struct regulator *reg = s_reg->regulator;
|
|
char supply[16];
|
|
int ret;
|
|
|
|
if (reg) {
|
|
refcount_inc(&s_reg->refcount);
|
|
return 0;
|
|
}
|
|
|
|
snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
|
|
reg = regulator_get(pctl->dev, supply);
|
|
if (IS_ERR(reg)) {
|
|
dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
|
|
'A' + bank);
|
|
return PTR_ERR(reg);
|
|
}
|
|
|
|
ret = regulator_enable(reg);
|
|
if (ret) {
|
|
dev_err(pctl->dev,
|
|
"Couldn't enable bank P%c regulator\n", 'A' + bank);
|
|
goto out;
|
|
}
|
|
|
|
sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
|
|
|
|
s_reg->regulator = reg;
|
|
refcount_set(&s_reg->refcount, 1);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
regulator_put(s_reg->regulator);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned short bank = offset / PINS_PER_BANK;
|
|
unsigned short bank_offset = bank - pctl->desc->pin_base /
|
|
PINS_PER_BANK;
|
|
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
|
|
|
|
if (!refcount_dec_and_test(&s_reg->refcount))
|
|
return 0;
|
|
|
|
regulator_disable(s_reg->regulator);
|
|
regulator_put(s_reg->regulator);
|
|
s_reg->regulator = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinmux_ops sunxi_pmx_ops = {
|
|
.get_functions_count = sunxi_pmx_get_funcs_cnt,
|
|
.get_function_name = sunxi_pmx_get_func_name,
|
|
.get_function_groups = sunxi_pmx_get_func_groups,
|
|
.set_mux = sunxi_pmx_set_mux,
|
|
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
|
|
.request = sunxi_pmx_request,
|
|
.free = sunxi_pmx_free,
|
|
.strict = true,
|
|
};
|
|
|
|
static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
|
|
unsigned offset)
|
|
{
|
|
return pinctrl_gpio_direction_input(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
bool set_mux = pctl->desc->irq_read_needs_mux &&
|
|
gpiochip_line_is_irq(chip, offset);
|
|
u32 pin = offset + chip->base;
|
|
u32 val;
|
|
|
|
if (set_mux)
|
|
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
|
|
|
|
val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
|
|
|
|
if (set_mux)
|
|
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
|
|
|
|
return !!val;
|
|
}
|
|
|
|
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
unsigned long flags;
|
|
u32 regval;
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
regval = readl(pctl->membase + reg);
|
|
|
|
if (value)
|
|
regval |= BIT(index);
|
|
else
|
|
regval &= ~(BIT(index));
|
|
|
|
writel(regval, pctl->membase + reg);
|
|
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
sunxi_pinctrl_gpio_set(chip, offset, value);
|
|
return pinctrl_gpio_direction_output(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec,
|
|
u32 *flags)
|
|
{
|
|
int pin, base;
|
|
|
|
base = PINS_PER_BANK * gpiospec->args[0];
|
|
pin = base + gpiospec->args[1];
|
|
|
|
if (pin > gc->ngpio)
|
|
return -EINVAL;
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[2];
|
|
|
|
return pin;
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
|
|
struct sunxi_desc_function *desc;
|
|
unsigned pinnum = pctl->desc->pin_base + offset;
|
|
unsigned irqnum;
|
|
|
|
if (offset >= chip->ngpio)
|
|
return -ENXIO;
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
|
|
|
|
dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
|
|
chip->label, offset + chip->base, irqnum);
|
|
|
|
return irq_find_mapping(pctl->domain, irqnum);
|
|
}
|
|
|
|
static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
struct sunxi_desc_function *func;
|
|
int ret;
|
|
|
|
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
|
|
pctl->irq_array[d->hwirq], "irq");
|
|
if (!func)
|
|
return -EINVAL;
|
|
|
|
ret = gpiochip_lock_as_irq(pctl->chip,
|
|
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
|
|
if (ret) {
|
|
dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
|
|
irqd_to_hwirq(d));
|
|
return ret;
|
|
}
|
|
|
|
/* Change muxing to INT mode */
|
|
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
|
|
gpiochip_unlock_as_irq(pctl->chip,
|
|
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
|
|
}
|
|
|
|
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
|
|
u8 index = sunxi_irq_cfg_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 regval;
|
|
u8 mode;
|
|
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
mode = IRQ_EDGE_RISING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
mode = IRQ_EDGE_FALLING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
mode = IRQ_EDGE_BOTH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
mode = IRQ_LEVEL_HIGH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
mode = IRQ_LEVEL_LOW;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
if (type & IRQ_TYPE_LEVEL_MASK)
|
|
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
|
|
handle_fasteoi_irq, NULL);
|
|
else
|
|
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
|
|
handle_edge_irq, NULL);
|
|
|
|
regval = readl(pctl->membase + reg);
|
|
regval &= ~(IRQ_CFG_IRQ_MASK << index);
|
|
writel(regval | (mode << index), pctl->membase + reg);
|
|
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_ack(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
|
|
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
|
|
|
|
/* Clear the IRQ */
|
|
writel(1 << status_idx, pctl->membase + status_reg);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Mask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val & ~(1 << idx), pctl->membase + reg);
|
|
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
raw_spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Unmask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val | (1 << idx), pctl->membase + reg);
|
|
|
|
raw_spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
|
|
{
|
|
sunxi_pinctrl_irq_ack(d);
|
|
sunxi_pinctrl_irq_unmask(d);
|
|
}
|
|
|
|
static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
|
|
.name = "sunxi_pio_edge",
|
|
.irq_ack = sunxi_pinctrl_irq_ack,
|
|
.irq_mask = sunxi_pinctrl_irq_mask,
|
|
.irq_unmask = sunxi_pinctrl_irq_unmask,
|
|
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
|
|
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
|
|
.irq_set_type = sunxi_pinctrl_irq_set_type,
|
|
.flags = IRQCHIP_SKIP_SET_WAKE,
|
|
};
|
|
|
|
static struct irq_chip sunxi_pinctrl_level_irq_chip = {
|
|
.name = "sunxi_pio_level",
|
|
.irq_eoi = sunxi_pinctrl_irq_ack,
|
|
.irq_mask = sunxi_pinctrl_irq_mask,
|
|
.irq_unmask = sunxi_pinctrl_irq_unmask,
|
|
/* Define irq_enable / disable to avoid spurious irqs for drivers
|
|
* using these to suppress irqs while they clear the irq source */
|
|
.irq_enable = sunxi_pinctrl_irq_ack_unmask,
|
|
.irq_disable = sunxi_pinctrl_irq_mask,
|
|
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
|
|
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
|
|
.irq_set_type = sunxi_pinctrl_irq_set_type,
|
|
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
|
|
IRQCHIP_EOI_IF_HANDLED,
|
|
};
|
|
|
|
static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
|
|
struct device_node *node,
|
|
const u32 *intspec,
|
|
unsigned int intsize,
|
|
unsigned long *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
struct sunxi_pinctrl *pctl = d->host_data;
|
|
struct sunxi_desc_function *desc;
|
|
int pin, base;
|
|
|
|
if (intsize < 3)
|
|
return -EINVAL;
|
|
|
|
base = PINS_PER_BANK * intspec[0];
|
|
pin = pctl->desc->pin_base + base + intspec[1];
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
*out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
|
|
*out_type = intspec[2];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
|
|
.xlate = sunxi_pinctrl_irq_of_xlate,
|
|
};
|
|
|
|
static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
|
|
{
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
|
|
unsigned long bank, reg, val;
|
|
|
|
for (bank = 0; bank < pctl->desc->irq_banks; bank++)
|
|
if (irq == pctl->irq[bank])
|
|
break;
|
|
|
|
if (bank == pctl->desc->irq_banks)
|
|
return;
|
|
|
|
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
|
|
val = readl(pctl->membase + reg);
|
|
|
|
if (val) {
|
|
int irqoffset;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
|
|
int pin_irq = irq_find_mapping(pctl->domain,
|
|
bank * IRQ_PER_BANK + irqoffset);
|
|
generic_handle_irq(pin_irq);
|
|
}
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
}
|
|
|
|
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
|
|
const char *name)
|
|
{
|
|
struct sunxi_pinctrl_function *func = pctl->functions;
|
|
|
|
while (func->name) {
|
|
/* function already there */
|
|
if (strcmp(func->name, name) == 0) {
|
|
func->ngroups++;
|
|
return -EEXIST;
|
|
}
|
|
func++;
|
|
}
|
|
|
|
func->name = name;
|
|
func->ngroups = 1;
|
|
|
|
pctl->nfunctions++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
|
|
void *ptr;
|
|
int i;
|
|
|
|
/*
|
|
* Allocate groups
|
|
*
|
|
* We assume that the number of groups is the number of pins
|
|
* given in the data array.
|
|
|
|
* This will not always be true, since some pins might not be
|
|
* available in the current variant, but fortunately for us,
|
|
* this means that the number of pins is the maximum group
|
|
* number we will ever see.
|
|
*/
|
|
pctl->groups = devm_kcalloc(&pdev->dev,
|
|
pctl->desc->npins, sizeof(*pctl->groups),
|
|
GFP_KERNEL);
|
|
if (!pctl->groups)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
|
|
|
|
if (pin->variant && !(pctl->variant & pin->variant))
|
|
continue;
|
|
|
|
group->name = pin->pin.name;
|
|
group->pin = pin->pin.number;
|
|
|
|
/* And now we count the actual number of pins / groups */
|
|
pctl->ngroups++;
|
|
}
|
|
|
|
/*
|
|
* We suppose that we won't have any more functions than pins,
|
|
* we'll reallocate that later anyway
|
|
*/
|
|
pctl->functions = kcalloc(pctl->ngroups,
|
|
sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
if (!pctl->functions)
|
|
return -ENOMEM;
|
|
|
|
/* Count functions and their associated groups */
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func;
|
|
|
|
if (pin->variant && !(pctl->variant & pin->variant))
|
|
continue;
|
|
|
|
for (func = pin->functions; func->name; func++) {
|
|
if (func->variant && !(pctl->variant & func->variant))
|
|
continue;
|
|
|
|
/* Create interrupt mapping while we're at it */
|
|
if (!strcmp(func->name, "irq")) {
|
|
int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
|
|
pctl->irq_array[irqnum] = pin->pin.number;
|
|
}
|
|
|
|
sunxi_pinctrl_add_function(pctl, func->name);
|
|
}
|
|
}
|
|
|
|
/* And now allocated and fill the array for real */
|
|
ptr = krealloc(pctl->functions,
|
|
pctl->nfunctions * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
if (!ptr) {
|
|
kfree(pctl->functions);
|
|
pctl->functions = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
pctl->functions = ptr;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func;
|
|
|
|
if (pin->variant && !(pctl->variant & pin->variant))
|
|
continue;
|
|
|
|
for (func = pin->functions; func->name; func++) {
|
|
struct sunxi_pinctrl_function *func_item;
|
|
const char **func_grp;
|
|
|
|
if (func->variant && !(pctl->variant & func->variant))
|
|
continue;
|
|
|
|
func_item = sunxi_pinctrl_find_function_by_name(pctl,
|
|
func->name);
|
|
if (!func_item) {
|
|
kfree(pctl->functions);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!func_item->groups) {
|
|
func_item->groups =
|
|
devm_kcalloc(&pdev->dev,
|
|
func_item->ngroups,
|
|
sizeof(*func_item->groups),
|
|
GFP_KERNEL);
|
|
if (!func_item->groups) {
|
|
kfree(pctl->functions);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
func_grp = func_item->groups;
|
|
while (*func_grp)
|
|
func_grp++;
|
|
|
|
*func_grp = pin->pin.name;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
|
|
{
|
|
unsigned long clock = clk_get_rate(clk);
|
|
unsigned int best_diff, best_div;
|
|
int i;
|
|
|
|
best_diff = abs(freq - clock);
|
|
best_div = 0;
|
|
|
|
for (i = 1; i < 8; i++) {
|
|
int cur_diff = abs(freq - (clock >> i));
|
|
|
|
if (cur_diff < best_diff) {
|
|
best_diff = cur_diff;
|
|
best_div = i;
|
|
}
|
|
}
|
|
|
|
*diff = best_diff;
|
|
return best_div;
|
|
}
|
|
|
|
static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
|
|
struct device_node *node)
|
|
{
|
|
unsigned int hosc_diff, losc_diff;
|
|
unsigned int hosc_div, losc_div;
|
|
struct clk *hosc, *losc;
|
|
u8 div, src;
|
|
int i, ret;
|
|
|
|
/* Deal with old DTs that didn't have the oscillators */
|
|
if (of_clk_get_parent_count(node) != 3)
|
|
return 0;
|
|
|
|
/* If we don't have any setup, bail out */
|
|
if (!of_find_property(node, "input-debounce", NULL))
|
|
return 0;
|
|
|
|
losc = devm_clk_get(pctl->dev, "losc");
|
|
if (IS_ERR(losc))
|
|
return PTR_ERR(losc);
|
|
|
|
hosc = devm_clk_get(pctl->dev, "hosc");
|
|
if (IS_ERR(hosc))
|
|
return PTR_ERR(hosc);
|
|
|
|
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
|
unsigned long debounce_freq;
|
|
u32 debounce;
|
|
|
|
ret = of_property_read_u32_index(node, "input-debounce",
|
|
i, &debounce);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!debounce)
|
|
continue;
|
|
|
|
debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
|
|
losc_div = sunxi_pinctrl_get_debounce_div(losc,
|
|
debounce_freq,
|
|
&losc_diff);
|
|
|
|
hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
|
|
debounce_freq,
|
|
&hosc_diff);
|
|
|
|
if (hosc_diff < losc_diff) {
|
|
div = hosc_div;
|
|
src = 1;
|
|
} else {
|
|
div = losc_div;
|
|
src = 0;
|
|
}
|
|
|
|
writel(src | div << 4,
|
|
pctl->membase +
|
|
sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
|
|
const struct sunxi_pinctrl_desc *desc,
|
|
unsigned long variant)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct pinctrl_desc *pctrl_desc;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct sunxi_pinctrl *pctl;
|
|
struct pinmux_ops *pmxops;
|
|
struct resource *res;
|
|
int i, ret, last_pin, pin_idx;
|
|
struct clk *clk;
|
|
|
|
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
|
if (!pctl)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, pctl);
|
|
|
|
raw_spin_lock_init(&pctl->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pctl->membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pctl->membase))
|
|
return PTR_ERR(pctl->membase);
|
|
|
|
pctl->dev = &pdev->dev;
|
|
pctl->desc = desc;
|
|
pctl->variant = variant;
|
|
|
|
pctl->irq_array = devm_kcalloc(&pdev->dev,
|
|
IRQ_PER_BANK * pctl->desc->irq_banks,
|
|
sizeof(*pctl->irq_array),
|
|
GFP_KERNEL);
|
|
if (!pctl->irq_array)
|
|
return -ENOMEM;
|
|
|
|
ret = sunxi_pinctrl_build_state(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pins = devm_kcalloc(&pdev->dev,
|
|
pctl->desc->npins, sizeof(*pins),
|
|
GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
if (pin->variant && !(pctl->variant & pin->variant))
|
|
continue;
|
|
|
|
pins[pin_idx++] = pin->pin;
|
|
}
|
|
|
|
pctrl_desc = devm_kzalloc(&pdev->dev,
|
|
sizeof(*pctrl_desc),
|
|
GFP_KERNEL);
|
|
if (!pctrl_desc)
|
|
return -ENOMEM;
|
|
|
|
pctrl_desc->name = dev_name(&pdev->dev);
|
|
pctrl_desc->owner = THIS_MODULE;
|
|
pctrl_desc->pins = pins;
|
|
pctrl_desc->npins = pctl->ngroups;
|
|
pctrl_desc->confops = &sunxi_pconf_ops;
|
|
pctrl_desc->pctlops = &sunxi_pctrl_ops;
|
|
|
|
pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
|
|
GFP_KERNEL);
|
|
if (!pmxops)
|
|
return -ENOMEM;
|
|
|
|
if (desc->disable_strict_mode)
|
|
pmxops->strict = false;
|
|
|
|
pctrl_desc->pmxops = pmxops;
|
|
|
|
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
|
|
if (IS_ERR(pctl->pctl_dev)) {
|
|
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
|
return PTR_ERR(pctl->pctl_dev);
|
|
}
|
|
|
|
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
|
|
if (!pctl->chip)
|
|
return -ENOMEM;
|
|
|
|
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
|
|
pctl->chip->owner = THIS_MODULE;
|
|
pctl->chip->request = gpiochip_generic_request,
|
|
pctl->chip->free = gpiochip_generic_free,
|
|
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
|
|
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
|
|
pctl->chip->get = sunxi_pinctrl_gpio_get,
|
|
pctl->chip->set = sunxi_pinctrl_gpio_set,
|
|
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
|
|
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
|
|
pctl->chip->of_gpio_n_cells = 3,
|
|
pctl->chip->can_sleep = false,
|
|
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
|
|
pctl->desc->pin_base;
|
|
pctl->chip->label = dev_name(&pdev->dev);
|
|
pctl->chip->parent = &pdev->dev;
|
|
pctl->chip->base = pctl->desc->pin_base;
|
|
|
|
ret = gpiochip_add_data(pctl->chip, pctl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
|
|
pin->pin.number - pctl->desc->pin_base,
|
|
pin->pin.number, 1);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
ret = of_clk_get_parent_count(node);
|
|
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
|
|
pctl->irq = devm_kcalloc(&pdev->dev,
|
|
pctl->desc->irq_banks,
|
|
sizeof(*pctl->irq),
|
|
GFP_KERNEL);
|
|
if (!pctl->irq) {
|
|
ret = -ENOMEM;
|
|
goto clk_error;
|
|
}
|
|
|
|
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
|
pctl->irq[i] = platform_get_irq(pdev, i);
|
|
if (pctl->irq[i] < 0) {
|
|
ret = pctl->irq[i];
|
|
goto clk_error;
|
|
}
|
|
}
|
|
|
|
pctl->domain = irq_domain_add_linear(node,
|
|
pctl->desc->irq_banks * IRQ_PER_BANK,
|
|
&sunxi_pinctrl_irq_domain_ops,
|
|
pctl);
|
|
if (!pctl->domain) {
|
|
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
|
|
ret = -ENOMEM;
|
|
goto clk_error;
|
|
}
|
|
|
|
for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
|
|
int irqno = irq_create_mapping(pctl->domain, i);
|
|
|
|
irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
|
|
handle_edge_irq);
|
|
irq_set_chip_data(irqno, pctl);
|
|
}
|
|
|
|
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
|
/* Mask and clear all IRQs before registering a handler */
|
|
writel(0, pctl->membase +
|
|
sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
|
|
writel(0xffffffff,
|
|
pctl->membase +
|
|
sunxi_irq_status_reg_from_bank(pctl->desc, i));
|
|
|
|
irq_set_chained_handler_and_data(pctl->irq[i],
|
|
sunxi_pinctrl_irq_handler,
|
|
pctl);
|
|
}
|
|
|
|
sunxi_pinctrl_setup_debounce(pctl, node);
|
|
|
|
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
|
|
|
|
return 0;
|
|
|
|
clk_error:
|
|
clk_disable_unprepare(clk);
|
|
gpiochip_error:
|
|
gpiochip_remove(pctl->chip);
|
|
return ret;
|
|
}
|