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89d63fe179
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* Board specific pci fixups.
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/jmr3927.h>
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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unsigned char irq = pin;
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/* IRQ rotation (PICMG) */
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irq--; /* 0-3 */
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if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
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/* PCI CardSlot (IDSEL=A23, DevNu=12) */
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/* PCIA => PCIC (IDSEL=A23) */
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/* NOTE: JMR3927 JP1 must be set to OPEN */
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irq = (irq + 2) % 4;
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} else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
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/* PCI CardSlot (IDSEL=A22, DevNu=11) */
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/* PCIA => PCIA (IDSEL=A22) */
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/* NOTE: JMR3927 JP1 must be set to OPEN */
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irq = (irq + 0) % 4;
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} else {
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/* PCI Backplane */
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if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
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irq = (irq + 33 - slot) % 4;
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else
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irq = (irq + 3 + slot) % 4;
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}
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irq++; /* 1-4 */
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switch (irq) {
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case 1:
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irq = JMR3927_IRQ_IOC_PCIA;
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break;
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case 2:
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irq = JMR3927_IRQ_IOC_PCIB;
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break;
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case 3:
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irq = JMR3927_IRQ_IOC_PCIC;
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break;
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case 4:
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irq = JMR3927_IRQ_IOC_PCID;
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break;
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}
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/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
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if (dev->bus->parent == NULL &&
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slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24))
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irq = JMR3927_IRQ_ETHER0;
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return irq;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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