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881730ad36
Expose cpu cache topology via sysfs. The created sysfs directory structure is compatible to what x86, ia64 and powerpc have. On s390 we expose only information about cpu caches which are private to a cpu via sysfs . Caches which are shared between cpus do not have a sysfs representation. The reason for that is that the file "shared_cpu_map" is mandatory and only if running under LPAR it is possible to tell which cpus share which cache. Second level hypervisors however do not and cannot expose that information to guests. In order to have a consistent view we made the choice to always only expose information about private cpu caches via sysfs. Example for a z196 cpu (cpu1 in /sys/devices/cpu): cpu1/cache/index0/size -- 64K cpu1/cache/index0/type -- Data cpu1/cache/index0/level -- 1 cpu1/cache/index0/number_of_sets -- 64 cpu1/cache/index0/shared_cpu_map -- 00000000,00000002 cpu1/cache/index0/shared_cpu_list -- 1 cpu1/cache/index0/coherency_line_size -- 256 cpu1/cache/index0/ways_of_associativity -- 4 cpu1/cache/index1/size -- 128K cpu1/cache/index1/type -- Instruction cpu1/cache/index1/level -- 1 cpu1/cache/index1/number_of_sets -- 64 cpu1/cache/index1/shared_cpu_map -- 00000000,00000002 cpu1/cache/index1/shared_cpu_list -- 1 cpu1/cache/index1/coherency_line_size -- 256 cpu1/cache/index1/ways_of_associativity -- 8 cpu1/cache/index2/size -- 1536K cpu1/cache/index2/type -- Unified cpu1/cache/index2/level -- 2 cpu1/cache/index2/number_of_sets -- 512 cpu1/cache/index2/shared_cpu_map -- 00000000,00000002 cpu1/cache/index2/shared_cpu_list -- 1 cpu1/cache/index2/coherency_line_size -- 256 cpu1/cache/index2/ways_of_associativity -- 12 Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> |
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| tile | ||
| um | ||
| unicore32 | ||
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