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b76032396d
Since the controller on R-Car Gen3 doesn't have any status registers
to detect initialization (LPSTS.SUSPM = 1) and the initialization needs
up to 45 usec, this patch adds wait after the initialization. Otherwise,
writing other registers (e.g. INTENB0) will fail.
Fixes: de18757e27 ("usb: renesas_usbhs: add R-Car Gen3 power control")
Cc: <stable@vger.kernel.org> # v4.6+
Cc: <balbi@kernel.org>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* Renesas USB driver R-Car Gen. 3 initialization and power control
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*
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* Copyright (C) 2016 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "common.h"
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#include "rcar3.h"
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#define LPSTS 0x102
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#define UGCTRL2 0x184 /* 32-bit register */
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/* Low Power Status register (LPSTS) */
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#define LPSTS_SUSPM 0x4000
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/* USB General control register 2 (UGCTRL2), bit[31:6] should be 0 */
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#define UGCTRL2_RESERVED_3 0x00000001 /* bit[3:0] should be B'0001 */
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#define UGCTRL2_USB0SEL_OTG 0x00000030
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static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data)
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{
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iowrite32(data, priv->base + reg);
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}
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static int usbhs_rcar3_power_ctrl(struct platform_device *pdev,
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void __iomem *base, int enable)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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usbhs_write32(priv, UGCTRL2, UGCTRL2_RESERVED_3 | UGCTRL2_USB0SEL_OTG);
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if (enable) {
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, LPSTS_SUSPM);
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/* The controller on R-Car Gen3 needs to wait up to 45 usec */
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udelay(45);
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} else {
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usbhs_bset(priv, LPSTS, LPSTS_SUSPM, 0);
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}
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return 0;
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}
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static int usbhs_rcar3_get_id(struct platform_device *pdev)
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{
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return USBHS_GADGET;
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}
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const struct renesas_usbhs_platform_callback usbhs_rcar3_ops = {
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.power_ctrl = usbhs_rcar3_power_ctrl,
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.get_id = usbhs_rcar3_get_id,
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};
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