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UART2 is used to connect the processor with the bluetooth chip, these pins are not common between IGEPv2 boards and IGEP COM MODULE boards. This patch muxes the correct pins for every board and removes UART2 configuration from common omap3-igep.dtsi file. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
123 lines
2.8 KiB
Plaintext
123 lines
2.8 KiB
Plaintext
/*
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* Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
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*
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* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
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* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "omap3-igep.dtsi"
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/ {
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model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
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compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&leds_pins>;
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compatible = "gpio-leds";
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boot {
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label = "omap3:green:boot";
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gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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user0 {
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label = "omap3:red:user0";
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gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
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default-state = "off";
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};
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user1 {
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label = "omap3:green:user1";
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gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
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default-state = "off";
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};
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user2 {
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label = "omap3:red:user1";
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gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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};
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&omap3_pmx_core {
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
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OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
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OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
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OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
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>;
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};
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};
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&omap3_pmx_core2 {
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leds_pins: pinmux_leds_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
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>;
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};
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};
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&gpmc {
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ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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linux,mtd-name= "micron,mt29c4g96maz";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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ti,nand-ecc-opt = "bch8";
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "SPL";
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reg = <0 0x100000>;
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};
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partition@80000 {
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label = "U-Boot";
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reg = <0x100000 0x180000>;
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};
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partition@1c0000 {
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label = "Environment";
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reg = <0x280000 0x100000>;
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};
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partition@280000 {
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label = "Kernel";
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reg = <0x380000 0x300000>;
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};
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partition@780000 {
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label = "Filesystem";
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reg = <0x680000 0x1f980000>;
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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};
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