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86be36f650
Yauheni Kaliuta pointed out that PTR_TO_STACK store/load verifier test
was failing on powerpc64 BE, and rightfully indicated that the PPC_LD()
macro is not masking away the last two bits of the offset per the ISA,
resulting in the generation of 'lwa' instruction instead of the intended
'ld' instruction.
Segher also pointed out that we can't simply mask away the last two bits
as that will result in loading/storing from/to a memory location that
was not intended.
This patch addresses this by using ldx/stdx if the offset is not
word-aligned. We load the offset into a temporary register (TMP_REG_2)
and use that as the index register in a subsequent ldx/stdx. We fix
PPC_LD() macro to mask off the last two bits, but enhance PPC_BPF_LL()
and PPC_BPF_STL() to factor in the offset value and generate the proper
instruction sequence. We also convert all existing users of PPC_LD() and
PPC_STD() to use these macros. All existing uses of these macros have
been audited to ensure that TMP_REG_2 can be clobbered.
Fixes: 156d0e290e ("powerpc/ebpf/jit: Implement JIT compiler for extended BPF")
Cc: stable@vger.kernel.org # v4.9+
Reported-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com>
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
145 lines
4.0 KiB
C
145 lines
4.0 KiB
C
/*
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* bpf_jit32.h: BPF JIT compiler for PPC
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*
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* Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
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*
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* Split from bpf_jit.h
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _BPF_JIT32_H
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#define _BPF_JIT32_H
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#include <asm/asm-compat.h>
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#include "bpf_jit.h"
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#ifdef CONFIG_PPC64
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#define BPF_PPC_STACK_R3_OFF 48
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#define BPF_PPC_STACK_LOCALS 32
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#define BPF_PPC_STACK_BASIC (48+64)
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#define BPF_PPC_STACK_SAVE (18*8)
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#define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
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BPF_PPC_STACK_SAVE)
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#define BPF_PPC_SLOWPATH_FRAME (48+64)
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#else
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#define BPF_PPC_STACK_R3_OFF 24
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#define BPF_PPC_STACK_LOCALS 16
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#define BPF_PPC_STACK_BASIC (24+32)
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#define BPF_PPC_STACK_SAVE (18*4)
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#define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
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BPF_PPC_STACK_SAVE)
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#define BPF_PPC_SLOWPATH_FRAME (24+32)
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#endif
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#define REG_SZ (BITS_PER_LONG/8)
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/*
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* Generated code register usage:
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*
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* As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
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*
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* skb r3 (Entry parameter)
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* A register r4
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* X register r5
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* addr param r6
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* r7-r10 scratch
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* skb->data r14
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* skb headlen r15 (skb->len - skb->data_len)
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* m[0] r16
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* m[...] ...
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* m[15] r31
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*/
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#define r_skb 3
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#define r_ret 3
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#define r_A 4
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#define r_X 5
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#define r_addr 6
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#define r_scratch1 7
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#define r_scratch2 8
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#define r_D 14
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#define r_HL 15
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#define r_M 16
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#ifndef __ASSEMBLY__
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/*
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* Assembly helpers from arch/powerpc/net/bpf_jit.S:
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*/
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#define DECLARE_LOAD_FUNC(func) \
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extern u8 func[], func##_negative_offset[], func##_positive_offset[]
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DECLARE_LOAD_FUNC(sk_load_word);
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DECLARE_LOAD_FUNC(sk_load_half);
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DECLARE_LOAD_FUNC(sk_load_byte);
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DECLARE_LOAD_FUNC(sk_load_byte_msh);
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#define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LBZ(r, r, IMM_L(i)); } } while(0)
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#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LD(r, r, IMM_L(i)); } } while(0)
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#define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LWZ(r, r, IMM_L(i)); } } while(0)
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#define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \
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else { PPC_ADDIS(r, base, IMM_HA(i)); \
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PPC_LHZ(r, r, IMM_L(i)); } } while(0)
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#ifdef CONFIG_PPC64
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#define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0)
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#else
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#define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0)
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#endif
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#ifdef CONFIG_SMP
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#ifdef CONFIG_PPC64
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#define PPC_BPF_LOAD_CPU(r) \
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do { BUILD_BUG_ON(FIELD_SIZEOF(struct paca_struct, paca_index) != 2); \
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PPC_LHZ_OFFS(r, 13, offsetof(struct paca_struct, paca_index)); \
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} while (0)
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#else
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#define PPC_BPF_LOAD_CPU(r) \
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do { BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4); \
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PPC_LHZ_OFFS(r, (1 & ~(THREAD_SIZE - 1)), \
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offsetof(struct thread_info, cpu)); \
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} while(0)
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#endif
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#else
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#define PPC_BPF_LOAD_CPU(r) do { PPC_LI(r, 0); } while(0)
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#endif
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#define PPC_LHBRX_OFFS(r, base, i) \
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do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
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#ifdef __LITTLE_ENDIAN__
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#define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
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#else
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#define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
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#endif
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#define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0)
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#define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0)
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#define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0)
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#define SEEN_DATAREF 0x10000 /* might call external helpers */
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#define SEEN_XREG 0x20000 /* X reg is used */
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#define SEEN_MEM 0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
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* storage */
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#define SEEN_MEM_MSK 0x0ffff
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struct codegen_context {
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unsigned int seen;
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unsigned int idx;
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int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
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};
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#endif
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#endif
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