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bcd61c0f53
Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
292 lines
6.5 KiB
C
292 lines
6.5 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <asm/div64.h>
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#include "clk-rcg.h"
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#define CMD_REG 0x0
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#define CMD_UPDATE BIT(0)
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#define CMD_ROOT_EN BIT(1)
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#define CMD_DIRTY_CFG BIT(4)
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#define CMD_DIRTY_N BIT(5)
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#define CMD_DIRTY_M BIT(6)
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#define CMD_DIRTY_D BIT(7)
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#define CMD_ROOT_OFF BIT(31)
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#define CFG_REG 0x4
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#define CFG_SRC_DIV_SHIFT 0
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#define CFG_SRC_SEL_SHIFT 8
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#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
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#define CFG_MODE_SHIFT 12
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#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
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#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
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#define M_REG 0x8
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#define N_REG 0xc
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#define D_REG 0x10
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static int clk_rcg2_is_enabled(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cmd;
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int ret;
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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return (cmd & CMD_ROOT_OFF) != 0;
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}
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static u8 clk_rcg2_get_parent(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 cfg;
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int i, ret;
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
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if (ret)
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return ret;
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cfg &= CFG_SRC_SEL_MASK;
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cfg >>= CFG_SRC_SEL_SHIFT;
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for (i = 0; i < num_parents; i++)
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if (cfg == rcg->parent_map[i])
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return i;
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return -EINVAL;
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}
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static int update_config(struct clk_rcg2 *rcg)
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{
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int count, ret;
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u32 cmd;
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struct clk_hw *hw = &rcg->clkr.hw;
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const char *name = __clk_get_name(hw->clk);
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
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CMD_UPDATE, CMD_UPDATE);
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if (ret)
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return ret;
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/* Wait for update to take effect */
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for (count = 500; count > 0; count--) {
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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if (!(cmd & CMD_UPDATE))
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return 0;
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udelay(1);
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}
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WARN(1, "%s: rcg didn't update its configuration.", name);
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return 0;
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}
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static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int ret;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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CFG_SRC_SEL_MASK,
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rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
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if (ret)
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return ret;
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return update_config(rcg);
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}
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/*
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* Calculate m/n:d rate
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*
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* parent_rate m
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* rate = ----------- x ---
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* hid_div n
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*/
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static unsigned long
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calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
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{
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if (hid_div) {
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rate *= 2;
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rate /= hid_div + 1;
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}
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if (mode) {
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u64 tmp = rate;
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tmp *= m;
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do_div(tmp, n);
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rate = tmp;
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}
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return rate;
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}
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static unsigned long
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clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
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if (rcg->mnd_width) {
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mask = BIT(rcg->mnd_width) - 1;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
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m &= mask;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
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n = ~n;
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n &= mask;
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n += m;
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mode = cfg & CFG_MODE_MASK;
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mode >>= CFG_MODE_SHIFT;
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}
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mask = BIT(rcg->hid_width) - 1;
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hid_div = cfg >> CFG_SRC_DIV_SHIFT;
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hid_div &= mask;
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return calc_rate(parent_rate, m, n, mode, hid_div);
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}
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static const
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struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
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{
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if (!f)
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return NULL;
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for (; f->freq; f++)
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if (rate <= f->freq)
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return f;
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return NULL;
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}
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static long _freq_tbl_determine_rate(struct clk_hw *hw,
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const struct freq_tbl *f, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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unsigned long clk_flags;
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f = find_freq(f, rate);
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if (!f)
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return -EINVAL;
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clk_flags = __clk_get_flags(hw->clk);
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*p = clk_get_parent_by_index(hw->clk, f->src);
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if (clk_flags & CLK_SET_RATE_PARENT) {
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if (f->pre_div) {
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rate /= 2;
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rate *= f->pre_div + 1;
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}
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if (f->n) {
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u64 tmp = rate;
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tmp = tmp * f->n;
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do_div(tmp, f->m);
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rate = tmp;
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}
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} else {
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rate = __clk_get_rate(*p);
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}
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*p_rate = rate;
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return f->freq;
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}
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static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *p_rate, struct clk **p)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
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}
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f;
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u32 cfg, mask;
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int ret;
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f = find_freq(rcg->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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if (rcg->mnd_width && f->n) {
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mask = BIT(rcg->mnd_width) - 1;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
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mask, f->m);
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if (ret)
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return ret;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
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mask, ~(f->n - f->m));
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if (ret)
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return ret;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
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mask, ~f->n);
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if (ret)
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return ret;
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}
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mask = BIT(rcg->hid_width) - 1;
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mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
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cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
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cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
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if (rcg->mnd_width && f->n)
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cfg |= CFG_MODE_DUAL_EDGE;
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
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cfg);
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if (ret)
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return ret;
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return update_config(rcg);
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}
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static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return __clk_rcg2_set_rate(hw, rate);
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}
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static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate, u8 index)
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{
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return __clk_rcg2_set_rate(hw, rate);
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}
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const struct clk_ops clk_rcg2_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.determine_rate = clk_rcg2_determine_rate,
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.set_rate = clk_rcg2_set_rate,
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.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_ops);
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