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e31cf2f4ca
Patch series "mm: consolidate definitions of page table accessors", v2. The low level page table accessors (pXY_index(), pXY_offset()) are duplicated across all architectures and sometimes more than once. For instance, we have 31 definition of pgd_offset() for 25 supported architectures. Most of these definitions are actually identical and typically it boils down to, e.g. static inline unsigned long pmd_index(unsigned long address) { return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); } static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) { return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address); } These definitions can be shared among 90% of the arches provided XYZ_SHIFT, PTRS_PER_XYZ and xyz_page_vaddr() are defined. For architectures that really need a custom version there is always possibility to override the generic version with the usual ifdefs magic. These patches introduce include/linux/pgtable.h that replaces include/asm-generic/pgtable.h and add the definitions of the page table accessors to the new header. This patch (of 12): The linux/mm.h header includes <asm/pgtable.h> to allow inlining of the functions involving page table manipulations, e.g. pte_alloc() and pmd_alloc(). So, there is no point to explicitly include <asm/pgtable.h> in the files that include <linux/mm.h>. The include statements in such cases are remove with a simple loop: for f in $(git grep -l "include <linux/mm.h>") ; do sed -i -e '/include <asm\/pgtable.h>/ d' $f done Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Mike Rapoport <rppt@kernel.org> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-1-rppt@kernel.org Link: http://lkml.kernel.org/r/20200514170327.31389-2-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
301 lines
7.3 KiB
C
301 lines
7.3 KiB
C
/*
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* Nios2 TLB handling
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*
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* Copyright (C) 2009, Wind River Systems Inc
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* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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#include <asm/cpuinfo.h>
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#define TLB_INDEX_MASK \
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((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
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<< PAGE_SHIFT)
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static void get_misc_and_pid(unsigned long *misc, unsigned long *pid)
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{
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*misc = RDCTL(CTL_TLBMISC);
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*misc &= (TLBMISC_PID | TLBMISC_WAY);
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*pid = *misc & TLBMISC_PID;
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}
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/*
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* This provides a PTEADDR value for addr that will cause a TLB miss
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* (fast TLB miss). TLB invalidation replaces entries with this value.
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*/
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static unsigned long pteaddr_invalid(unsigned long addr)
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{
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return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2;
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}
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/*
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* This one is only used for pages with the global bit set so we don't care
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* much about the ASID.
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*/
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static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsigned long tlbacc)
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{
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unsigned int way;
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unsigned long org_misc, pid_misc;
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/* remember pid/way until we return. */
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get_misc_and_pid(&org_misc, &pid_misc);
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WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
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for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
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unsigned long pteaddr;
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unsigned long tlbmisc;
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unsigned long pid;
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tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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pteaddr = RDCTL(CTL_PTEADDR);
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if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
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continue;
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tlbmisc = RDCTL(CTL_TLBMISC);
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pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
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if (pid != mmu_pid)
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continue;
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tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) | TLBMISC_WE |
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(way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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if (tlbacc == 0)
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WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
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WRCTL(CTL_TLBACC, tlbacc);
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/*
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* There should be only a single entry that maps a
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* particular {address,pid} so break after a match.
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*/
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break;
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}
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WRCTL(CTL_TLBMISC, org_misc);
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}
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static void flush_tlb_one_pid(unsigned long addr, unsigned long mmu_pid)
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{
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pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
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replace_tlb_one_pid(addr, mmu_pid, 0);
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}
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static void reload_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, pte_t pte)
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{
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pr_debug("Reload tlb-entry for vaddr=%#lx\n", addr);
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replace_tlb_one_pid(addr, mmu_pid, pte_val(pte));
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
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while (start < end) {
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flush_tlb_one_pid(start, mmu_pid);
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start += PAGE_SIZE;
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}
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}
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void reload_tlb_page(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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{
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unsigned long mmu_pid = get_pid_from_context(&vma->vm_mm->context);
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reload_tlb_one_pid(addr, mmu_pid, pte);
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}
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/*
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* This one is only used for pages with the global bit set so we don't care
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* much about the ASID.
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*/
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static void flush_tlb_one(unsigned long addr)
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{
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unsigned int way;
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unsigned long org_misc, pid_misc;
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pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr);
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/* remember pid/way until we return. */
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get_misc_and_pid(&org_misc, &pid_misc);
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WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2);
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for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
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unsigned long pteaddr;
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unsigned long tlbmisc;
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tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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pteaddr = RDCTL(CTL_PTEADDR);
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if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT))
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continue;
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pr_debug("Flush entry by writing way=%dl pid=%ld\n",
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way, (pid_misc >> TLBMISC_PID_SHIFT));
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tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
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WRCTL(CTL_TLBACC, 0);
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}
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WRCTL(CTL_TLBMISC, org_misc);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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while (start < end) {
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flush_tlb_one(start);
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start += PAGE_SIZE;
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}
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}
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void dump_tlb_line(unsigned long line)
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{
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unsigned int way;
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unsigned long org_misc;
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pr_debug("dump tlb-entries for line=%#lx (addr %08lx)\n", line,
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line << (PAGE_SHIFT + cpuinfo.tlb_num_ways_log2));
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/* remember pid/way until we return */
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org_misc = (RDCTL(CTL_TLBMISC) & (TLBMISC_PID | TLBMISC_WAY));
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WRCTL(CTL_PTEADDR, line << 2);
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for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
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unsigned long pteaddr;
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unsigned long tlbmisc;
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unsigned long tlbacc;
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WRCTL(CTL_TLBMISC, TLBMISC_RD | (way << TLBMISC_WAY_SHIFT));
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pteaddr = RDCTL(CTL_PTEADDR);
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tlbmisc = RDCTL(CTL_TLBMISC);
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tlbacc = RDCTL(CTL_TLBACC);
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if ((tlbacc << PAGE_SHIFT) != 0) {
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pr_debug("-- way:%02x vpn:0x%08lx phys:0x%08lx pid:0x%02lx flags:%c%c%c%c%c\n",
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way,
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(pteaddr << (PAGE_SHIFT-2)),
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(tlbacc << PAGE_SHIFT),
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((tlbmisc >> TLBMISC_PID_SHIFT) &
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TLBMISC_PID_MASK),
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(tlbacc & _PAGE_READ ? 'r' : '-'),
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(tlbacc & _PAGE_WRITE ? 'w' : '-'),
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(tlbacc & _PAGE_EXEC ? 'x' : '-'),
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(tlbacc & _PAGE_GLOBAL ? 'g' : '-'),
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(tlbacc & _PAGE_CACHED ? 'c' : '-'));
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}
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}
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WRCTL(CTL_TLBMISC, org_misc);
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}
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void dump_tlb(void)
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{
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unsigned int i;
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for (i = 0; i < cpuinfo.tlb_num_lines; i++)
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dump_tlb_line(i);
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}
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void flush_tlb_pid(unsigned long mmu_pid)
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{
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unsigned long addr = 0;
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unsigned int line;
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unsigned int way;
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unsigned long org_misc, pid_misc;
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/* remember pid/way until we return */
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get_misc_and_pid(&org_misc, &pid_misc);
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for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
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WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
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for (way = 0; way < cpuinfo.tlb_num_ways; way++) {
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unsigned long tlbmisc;
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unsigned long pid;
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tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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tlbmisc = RDCTL(CTL_TLBMISC);
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pid = (tlbmisc >> TLBMISC_PID_SHIFT) & TLBMISC_PID_MASK;
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if (pid != mmu_pid)
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continue;
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tlbmisc = TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
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WRCTL(CTL_TLBMISC, tlbmisc);
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WRCTL(CTL_TLBACC, 0);
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}
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addr += PAGE_SIZE;
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}
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WRCTL(CTL_TLBMISC, org_misc);
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}
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/*
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* All entries common to a mm share an asid. To effectively flush these
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* entries, we just bump the asid.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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if (current->mm == mm) {
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unsigned long mmu_pid = get_pid_from_context(&mm->context);
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flush_tlb_pid(mmu_pid);
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} else {
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memset(&mm->context, 0, sizeof(mm_context_t));
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}
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}
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void flush_tlb_all(void)
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{
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unsigned long addr = 0;
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unsigned int line;
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unsigned int way;
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unsigned long org_misc, pid_misc;
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/* remember pid/way until we return */
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get_misc_and_pid(&org_misc, &pid_misc);
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/* Start at way 0, way is auto-incremented after each TLBACC write */
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WRCTL(CTL_TLBMISC, TLBMISC_WE);
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/* Map each TLB entry to physcal address 0 with no-access and a
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bad ptbase */
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for (line = 0; line < cpuinfo.tlb_num_lines; line++) {
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WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));
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for (way = 0; way < cpuinfo.tlb_num_ways; way++)
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WRCTL(CTL_TLBACC, 0);
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addr += PAGE_SIZE;
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}
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/* restore pid/way */
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WRCTL(CTL_TLBMISC, org_misc);
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}
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void set_mmu_pid(unsigned long pid)
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{
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unsigned long tlbmisc;
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tlbmisc = RDCTL(CTL_TLBMISC);
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tlbmisc = (tlbmisc & TLBMISC_WAY);
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tlbmisc |= (pid & TLBMISC_PID_MASK) << TLBMISC_PID_SHIFT;
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WRCTL(CTL_TLBMISC, tlbmisc);
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}
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