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54c820d05e
1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAmAcDQgYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4kE48P/jSb7PhZYvEiPdjsPHxIEHa7 01Qc2gNDXkYkt+circ0NtDu3CH1DB5U2b5lITUy8McMM486N4vBNisPM3oId18ik lCinMehSGvlVxHmxOBEJAj6G/rLrw4lBflDHnV38WrzWgPU/DFXQQy0kjI92T5R5 YswWYG2skAU5GX3r8i8p8PibwlA3aH9aVpgE/iDsCbpljmpJktqVYkfijAuK8phP WVxBHQaa7N6KNxQmaVZtylz2GhtSwhx4omV/TNbJYFniLqzpTnFfxmkp161V1dL7 eUteuXwwmBpQAb/jYIilYEkLKBff6XTsl5wGzeIn2o/eAiD2jPUp6BOrxl87OXBM yd61mNP56aF1mgJ3bH6Qbs/qenSP5ptVKVSl983crzLCHpDOHX4ToG39TIGX6m9M o7vHYEZQznLKWcAJmV40oPDKuIaKbL9I0ZxTVSjK8Lw75kOfOssbztHQlJkMJHiG /2FF08Klk5oMP7SsUjVgasGqrVEamv1kkmtmK218tz2QJ6cksJsydvlwhxbIVvE6 mgH2WSVI+CRKakB4+bhCg5v1zl7tM4s5aUtoqz2cHxlMABt0mtvunoB9wt4LIIks z6V7myU05q5nGhD1ClmKU5F1Fnw1J6IIECb1lmrJSCOrl0mAWqlezVDSTu8v+7Yi 7rgviHqtdRoAdZSb1u6w =s8K8 -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.12 1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210204151750.7550-1-chunkuang.hu@kernel.org
854 lines
22 KiB
C
854 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include <linux/soc/mediatek/mtk-mutex.h>
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#include <asm/barrier.h>
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#include <soc/mediatek/smi.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_vblank.h>
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#include "mtk_drm_drv.h"
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_gem.h"
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#include "mtk_drm_plane.h"
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/*
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* struct mtk_drm_crtc - MediaTek specific crtc structure.
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* @base: crtc object.
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* @enabled: records whether crtc_enable succeeded
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* @planes: array of 4 drm_plane structures, one for each overlay plane
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* @pending_planes: whether any plane has pending changes to be applied
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* @mmsys_dev: pointer to the mmsys device for configuration registers
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* @mutex: handle to one of the ten disp_mutex streams
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* @ddp_comp_nr: number of components in ddp_comp
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* @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
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*
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* TODO: Needs update: this header is missing a bunch of member descriptions.
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*/
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struct mtk_drm_crtc {
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struct drm_crtc base;
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bool enabled;
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bool pending_needs_vblank;
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struct drm_pending_vblank_event *event;
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struct drm_plane *planes;
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unsigned int layer_nr;
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bool pending_planes;
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bool pending_async_planes;
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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struct cmdq_client *cmdq_client;
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u32 cmdq_event;
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#endif
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struct device *mmsys_dev;
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struct mtk_mutex *mutex;
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unsigned int ddp_comp_nr;
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struct mtk_ddp_comp **ddp_comp;
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/* lock for display hardware access */
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struct mutex hw_lock;
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};
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struct mtk_crtc_state {
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struct drm_crtc_state base;
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bool pending_config;
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unsigned int pending_width;
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unsigned int pending_height;
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unsigned int pending_vrefresh;
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};
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static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
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{
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return container_of(c, struct mtk_drm_crtc, base);
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}
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static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
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{
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return container_of(s, struct mtk_crtc_state, base);
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}
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static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
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{
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struct drm_crtc *crtc = &mtk_crtc->base;
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unsigned long flags;
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
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drm_crtc_vblank_put(crtc);
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mtk_crtc->event = NULL;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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}
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static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
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{
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drm_crtc_handle_vblank(&mtk_crtc->base);
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if (mtk_crtc->pending_needs_vblank) {
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mtk_drm_crtc_finish_page_flip(mtk_crtc);
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mtk_crtc->pending_needs_vblank = false;
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}
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}
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static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
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{
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struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
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mtk_mutex_put(mtk_crtc->mutex);
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drm_crtc_cleanup(crtc);
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}
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static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
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{
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struct mtk_crtc_state *state;
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if (crtc->state)
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__drm_atomic_helper_crtc_destroy_state(crtc->state);
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kfree(to_mtk_crtc_state(crtc->state));
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crtc->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state)
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__drm_atomic_helper_crtc_reset(crtc, &state->base);
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}
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static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
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{
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struct mtk_crtc_state *state;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return NULL;
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__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
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WARN_ON(state->base.crtc != crtc);
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state->base.crtc = crtc;
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return &state->base;
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}
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static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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__drm_atomic_helper_crtc_destroy_state(state);
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kfree(to_mtk_crtc_state(state));
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}
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static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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/* Nothing to do here, but this callback is mandatory. */
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return true;
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}
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static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
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state->pending_width = crtc->mode.hdisplay;
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state->pending_height = crtc->mode.vdisplay;
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state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
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wmb(); /* Make sure the above parameters are set before update */
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state->pending_config = true;
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}
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static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
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{
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int ret;
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int i;
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
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if (ret) {
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DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
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goto err;
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}
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}
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return 0;
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err:
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while (--i >= 0)
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mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
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return ret;
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}
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static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
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{
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int i;
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
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mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
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}
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static
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struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
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struct drm_plane *plane,
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unsigned int *local_layer)
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{
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struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
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struct mtk_ddp_comp *comp;
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int i, count = 0;
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unsigned int local_index = plane - mtk_crtc->planes;
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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comp = mtk_crtc->ddp_comp[i];
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if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
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*local_layer = local_index - count;
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return comp;
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}
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count += mtk_ddp_comp_layer_nr(comp);
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}
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WARN(1, "Failed to find component for plane %d\n", plane->index);
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return NULL;
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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static void ddp_cmdq_cb(struct cmdq_cb_data data)
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{
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cmdq_pkt_destroy(data.data);
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}
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#endif
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static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
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{
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struct drm_crtc *crtc = &mtk_crtc->base;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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struct drm_connector_list_iter conn_iter;
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unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
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int ret;
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int i;
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if (WARN_ON(!crtc->state))
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return -EINVAL;
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width = crtc->state->adjusted_mode.hdisplay;
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height = crtc->state->adjusted_mode.vdisplay;
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vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
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drm_for_each_encoder(encoder, crtc->dev) {
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if (encoder->crtc != crtc)
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continue;
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drm_connector_list_iter_begin(crtc->dev, &conn_iter);
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drm_for_each_connector_iter(connector, &conn_iter) {
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if (connector->encoder != encoder)
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continue;
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if (connector->display_info.bpc != 0 &&
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bpc > connector->display_info.bpc)
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bpc = connector->display_info.bpc;
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}
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drm_connector_list_iter_end(&conn_iter);
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}
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ret = pm_runtime_get_sync(crtc->dev->dev);
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if (ret < 0) {
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DRM_ERROR("Failed to enable power domain: %d\n", ret);
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return ret;
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}
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ret = mtk_mutex_prepare(mtk_crtc->mutex);
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if (ret < 0) {
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DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
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goto err_pm_runtime_put;
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}
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ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
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if (ret < 0) {
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DRM_ERROR("Failed to enable component clocks: %d\n", ret);
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goto err_mutex_unprepare;
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}
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for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
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mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
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mtk_crtc->ddp_comp[i]->id,
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mtk_crtc->ddp_comp[i + 1]->id);
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mtk_mutex_add_comp(mtk_crtc->mutex,
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mtk_crtc->ddp_comp[i]->id);
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}
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mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
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mtk_mutex_enable(mtk_crtc->mutex);
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
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if (i == 1)
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mtk_ddp_comp_bgclr_in_on(comp);
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mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
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mtk_ddp_comp_start(comp);
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}
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/* Initially configure all planes */
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *plane_state;
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struct mtk_ddp_comp *comp;
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unsigned int local_layer;
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plane_state = to_mtk_plane_state(plane->state);
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comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
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if (comp)
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mtk_ddp_comp_layer_config(comp, local_layer,
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plane_state, NULL);
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}
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return 0;
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err_mutex_unprepare:
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mtk_mutex_unprepare(mtk_crtc->mutex);
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err_pm_runtime_put:
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pm_runtime_put(crtc->dev->dev);
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return ret;
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}
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static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
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{
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struct drm_device *drm = mtk_crtc->base.dev;
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struct drm_crtc *crtc = &mtk_crtc->base;
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int i;
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
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if (i == 1)
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mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
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}
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
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mtk_mutex_remove_comp(mtk_crtc->mutex,
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mtk_crtc->ddp_comp[i]->id);
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mtk_mutex_disable(mtk_crtc->mutex);
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for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
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mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
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mtk_crtc->ddp_comp[i]->id,
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mtk_crtc->ddp_comp[i + 1]->id);
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mtk_mutex_remove_comp(mtk_crtc->mutex,
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mtk_crtc->ddp_comp[i]->id);
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}
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mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
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mtk_crtc_ddp_clk_disable(mtk_crtc);
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mtk_mutex_unprepare(mtk_crtc->mutex);
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pm_runtime_put(drm->dev);
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if (crtc->state->event && !crtc->state->active) {
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spin_lock_irq(&crtc->dev->event_lock);
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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crtc->state->event = NULL;
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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}
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static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
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struct cmdq_pkt *cmdq_handle)
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{
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struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
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struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
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struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
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unsigned int i;
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unsigned int local_layer;
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/*
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* TODO: instead of updating the registers here, we should prepare
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* working registers in atomic_commit and let the hardware command
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* queue update module registers on vblank.
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*/
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if (state->pending_config) {
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mtk_ddp_comp_config(comp, state->pending_width,
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state->pending_height,
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state->pending_vrefresh, 0,
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cmdq_handle);
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state->pending_config = false;
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}
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if (mtk_crtc->pending_planes) {
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *plane_state;
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plane_state = to_mtk_plane_state(plane->state);
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if (!plane_state->pending.config)
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continue;
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comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
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&local_layer);
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if (comp)
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mtk_ddp_comp_layer_config(comp, local_layer,
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plane_state,
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cmdq_handle);
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plane_state->pending.config = false;
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}
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mtk_crtc->pending_planes = false;
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}
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if (mtk_crtc->pending_async_planes) {
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *plane_state;
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plane_state = to_mtk_plane_state(plane->state);
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if (!plane_state->pending.async_config)
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continue;
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comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
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&local_layer);
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if (comp)
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mtk_ddp_comp_layer_config(comp, local_layer,
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plane_state,
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cmdq_handle);
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plane_state->pending.async_config = false;
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}
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mtk_crtc->pending_async_planes = false;
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}
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}
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static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
|
|
{
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
struct cmdq_pkt *cmdq_handle;
|
|
#endif
|
|
struct drm_crtc *crtc = &mtk_crtc->base;
|
|
struct mtk_drm_private *priv = crtc->dev->dev_private;
|
|
unsigned int pending_planes = 0, pending_async_planes = 0;
|
|
int i;
|
|
|
|
mutex_lock(&mtk_crtc->hw_lock);
|
|
for (i = 0; i < mtk_crtc->layer_nr; i++) {
|
|
struct drm_plane *plane = &mtk_crtc->planes[i];
|
|
struct mtk_plane_state *plane_state;
|
|
|
|
plane_state = to_mtk_plane_state(plane->state);
|
|
if (plane_state->pending.dirty) {
|
|
plane_state->pending.config = true;
|
|
plane_state->pending.dirty = false;
|
|
pending_planes |= BIT(i);
|
|
} else if (plane_state->pending.async_dirty) {
|
|
plane_state->pending.async_config = true;
|
|
plane_state->pending.async_dirty = false;
|
|
pending_async_planes |= BIT(i);
|
|
}
|
|
}
|
|
if (pending_planes)
|
|
mtk_crtc->pending_planes = true;
|
|
if (pending_async_planes)
|
|
mtk_crtc->pending_async_planes = true;
|
|
|
|
if (priv->data->shadow_register) {
|
|
mtk_mutex_acquire(mtk_crtc->mutex);
|
|
mtk_crtc_ddp_config(crtc, NULL);
|
|
mtk_mutex_release(mtk_crtc->mutex);
|
|
}
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
if (mtk_crtc->cmdq_client) {
|
|
mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
|
|
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
|
|
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
|
|
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
|
|
mtk_crtc_ddp_config(crtc, cmdq_handle);
|
|
cmdq_pkt_finalize(cmdq_handle);
|
|
cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
|
|
}
|
|
#endif
|
|
mutex_unlock(&mtk_crtc->hw_lock);
|
|
}
|
|
|
|
static void mtk_crtc_ddp_irq(void *data)
|
|
{
|
|
struct drm_crtc *crtc = data;
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
struct mtk_drm_private *priv = crtc->dev->dev_private;
|
|
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
|
|
#else
|
|
if (!priv->data->shadow_register)
|
|
#endif
|
|
mtk_crtc_ddp_config(crtc, NULL);
|
|
|
|
mtk_drm_finish_page_flip(mtk_crtc);
|
|
}
|
|
|
|
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
|
|
|
|
mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
|
|
|
|
mtk_ddp_comp_disable_vblank(comp);
|
|
}
|
|
|
|
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
|
|
struct mtk_plane_state *state)
|
|
{
|
|
unsigned int local_layer;
|
|
struct mtk_ddp_comp *comp;
|
|
|
|
comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
|
|
if (comp)
|
|
return mtk_ddp_comp_layer_check(comp, local_layer, state);
|
|
return 0;
|
|
}
|
|
|
|
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
|
|
struct drm_plane_state *new_state)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
const struct drm_plane_helper_funcs *plane_helper_funcs =
|
|
plane->helper_private;
|
|
|
|
if (!mtk_crtc->enabled)
|
|
return;
|
|
|
|
plane_helper_funcs->atomic_update(plane, new_state);
|
|
mtk_drm_crtc_hw_config(mtk_crtc);
|
|
}
|
|
|
|
static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
|
|
int ret;
|
|
|
|
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
|
|
|
|
ret = mtk_smi_larb_get(comp->larb_dev);
|
|
if (ret) {
|
|
DRM_ERROR("Failed to get larb: %d\n", ret);
|
|
return;
|
|
}
|
|
|
|
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
|
|
if (ret) {
|
|
mtk_smi_larb_put(comp->larb_dev);
|
|
return;
|
|
}
|
|
|
|
drm_crtc_vblank_on(crtc);
|
|
mtk_crtc->enabled = true;
|
|
}
|
|
|
|
static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
|
|
int i;
|
|
|
|
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
|
|
if (!mtk_crtc->enabled)
|
|
return;
|
|
|
|
/* Set all pending plane state to disabled */
|
|
for (i = 0; i < mtk_crtc->layer_nr; i++) {
|
|
struct drm_plane *plane = &mtk_crtc->planes[i];
|
|
struct mtk_plane_state *plane_state;
|
|
|
|
plane_state = to_mtk_plane_state(plane->state);
|
|
plane_state->pending.enable = false;
|
|
plane_state->pending.config = true;
|
|
}
|
|
mtk_crtc->pending_planes = true;
|
|
|
|
mtk_drm_crtc_hw_config(mtk_crtc);
|
|
/* Wait for planes to be disabled */
|
|
drm_crtc_wait_one_vblank(crtc);
|
|
|
|
drm_crtc_vblank_off(crtc);
|
|
mtk_crtc_ddp_hw_fini(mtk_crtc);
|
|
mtk_smi_larb_put(comp->larb_dev);
|
|
|
|
mtk_crtc->enabled = false;
|
|
}
|
|
|
|
static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
|
|
crtc);
|
|
struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
|
|
if (mtk_crtc->event && mtk_crtc_state->base.event)
|
|
DRM_ERROR("new event while there is still a pending event\n");
|
|
|
|
if (mtk_crtc_state->base.event) {
|
|
mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
mtk_crtc->event = mtk_crtc_state->base.event;
|
|
mtk_crtc_state->base.event = NULL;
|
|
}
|
|
}
|
|
|
|
static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
|
|
struct drm_atomic_state *state)
|
|
{
|
|
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
|
|
int i;
|
|
|
|
if (mtk_crtc->event)
|
|
mtk_crtc->pending_needs_vblank = true;
|
|
if (crtc->state->color_mgmt_changed)
|
|
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
|
|
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
|
|
mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
|
|
}
|
|
mtk_drm_crtc_hw_config(mtk_crtc);
|
|
}
|
|
|
|
static const struct drm_crtc_funcs mtk_crtc_funcs = {
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.destroy = mtk_drm_crtc_destroy,
|
|
.reset = mtk_drm_crtc_reset,
|
|
.atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
|
|
.atomic_destroy_state = mtk_drm_crtc_destroy_state,
|
|
.enable_vblank = mtk_drm_crtc_enable_vblank,
|
|
.disable_vblank = mtk_drm_crtc_disable_vblank,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
|
|
.mode_fixup = mtk_drm_crtc_mode_fixup,
|
|
.mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
|
|
.atomic_begin = mtk_drm_crtc_atomic_begin,
|
|
.atomic_flush = mtk_drm_crtc_atomic_flush,
|
|
.atomic_enable = mtk_drm_crtc_atomic_enable,
|
|
.atomic_disable = mtk_drm_crtc_atomic_disable,
|
|
};
|
|
|
|
static int mtk_drm_crtc_init(struct drm_device *drm,
|
|
struct mtk_drm_crtc *mtk_crtc,
|
|
unsigned int pipe)
|
|
{
|
|
struct drm_plane *primary = NULL;
|
|
struct drm_plane *cursor = NULL;
|
|
int i, ret;
|
|
|
|
for (i = 0; i < mtk_crtc->layer_nr; i++) {
|
|
if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
|
|
primary = &mtk_crtc->planes[i];
|
|
else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
|
|
cursor = &mtk_crtc->planes[i];
|
|
}
|
|
|
|
ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
|
|
&mtk_crtc_funcs, NULL);
|
|
if (ret)
|
|
goto err_cleanup_crtc;
|
|
|
|
drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
|
|
|
|
return 0;
|
|
|
|
err_cleanup_crtc:
|
|
drm_crtc_cleanup(&mtk_crtc->base);
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
|
|
int comp_idx)
|
|
{
|
|
struct mtk_ddp_comp *comp;
|
|
|
|
if (comp_idx > 1)
|
|
return 0;
|
|
|
|
comp = mtk_crtc->ddp_comp[comp_idx];
|
|
if (!comp->funcs)
|
|
return 0;
|
|
|
|
if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
|
|
return 0;
|
|
|
|
return mtk_ddp_comp_layer_nr(comp);
|
|
}
|
|
|
|
static inline
|
|
enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
|
|
unsigned int num_planes)
|
|
{
|
|
if (plane_idx == 0)
|
|
return DRM_PLANE_TYPE_PRIMARY;
|
|
else if (plane_idx == (num_planes - 1))
|
|
return DRM_PLANE_TYPE_CURSOR;
|
|
else
|
|
return DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
}
|
|
|
|
static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
|
|
struct mtk_drm_crtc *mtk_crtc,
|
|
int comp_idx, int pipe)
|
|
{
|
|
int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
|
|
struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
|
|
int i, ret;
|
|
|
|
for (i = 0; i < num_planes; i++) {
|
|
ret = mtk_plane_init(drm_dev,
|
|
&mtk_crtc->planes[mtk_crtc->layer_nr],
|
|
BIT(pipe),
|
|
mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
|
|
num_planes),
|
|
mtk_ddp_comp_supported_rotations(comp));
|
|
if (ret)
|
|
return ret;
|
|
|
|
mtk_crtc->layer_nr++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int mtk_drm_crtc_create(struct drm_device *drm_dev,
|
|
const enum mtk_ddp_comp_id *path, unsigned int path_len)
|
|
{
|
|
struct mtk_drm_private *priv = drm_dev->dev_private;
|
|
struct device *dev = drm_dev->dev;
|
|
struct mtk_drm_crtc *mtk_crtc;
|
|
unsigned int num_comp_planes = 0;
|
|
int pipe = priv->num_pipes;
|
|
int ret;
|
|
int i;
|
|
bool has_ctm = false;
|
|
uint gamma_lut_size = 0;
|
|
|
|
if (!path)
|
|
return 0;
|
|
|
|
for (i = 0; i < path_len; i++) {
|
|
enum mtk_ddp_comp_id comp_id = path[i];
|
|
struct device_node *node;
|
|
|
|
node = priv->comp_node[comp_id];
|
|
if (!node) {
|
|
dev_info(dev,
|
|
"Not creating crtc %d because component %d is disabled or missing\n",
|
|
pipe, comp_id);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
|
|
if (!mtk_crtc)
|
|
return -ENOMEM;
|
|
|
|
mtk_crtc->mmsys_dev = priv->mmsys_dev;
|
|
mtk_crtc->ddp_comp_nr = path_len;
|
|
mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
|
|
sizeof(*mtk_crtc->ddp_comp),
|
|
GFP_KERNEL);
|
|
if (!mtk_crtc->ddp_comp)
|
|
return -ENOMEM;
|
|
|
|
mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
|
|
if (IS_ERR(mtk_crtc->mutex)) {
|
|
ret = PTR_ERR(mtk_crtc->mutex);
|
|
dev_err(dev, "Failed to get mutex: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
|
|
enum mtk_ddp_comp_id comp_id = path[i];
|
|
struct mtk_ddp_comp *comp;
|
|
struct device_node *node;
|
|
|
|
node = priv->comp_node[comp_id];
|
|
comp = &priv->ddp_comp[comp_id];
|
|
if (!comp) {
|
|
dev_err(dev, "Component %pOF not initialized\n", node);
|
|
ret = -ENODEV;
|
|
return ret;
|
|
}
|
|
|
|
mtk_crtc->ddp_comp[i] = comp;
|
|
|
|
if (comp->funcs) {
|
|
if (comp->funcs->gamma_set)
|
|
gamma_lut_size = MTK_LUT_SIZE;
|
|
|
|
if (comp->funcs->ctm_set)
|
|
has_ctm = true;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
|
|
num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
|
|
|
|
mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
|
|
sizeof(struct drm_plane), GFP_KERNEL);
|
|
|
|
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
|
|
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
|
|
pipe);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (gamma_lut_size)
|
|
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
|
|
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
|
|
priv->num_pipes++;
|
|
mutex_init(&mtk_crtc->hw_lock);
|
|
|
|
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
|
|
mtk_crtc->cmdq_client =
|
|
cmdq_mbox_create(mtk_crtc->mmsys_dev,
|
|
drm_crtc_index(&mtk_crtc->base));
|
|
if (IS_ERR(mtk_crtc->cmdq_client)) {
|
|
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
|
|
drm_crtc_index(&mtk_crtc->base));
|
|
mtk_crtc->cmdq_client = NULL;
|
|
}
|
|
|
|
if (mtk_crtc->cmdq_client) {
|
|
ret = of_property_read_u32_index(priv->mutex_node,
|
|
"mediatek,gce-events",
|
|
drm_crtc_index(&mtk_crtc->base),
|
|
&mtk_crtc->cmdq_event);
|
|
if (ret) {
|
|
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
|
|
drm_crtc_index(&mtk_crtc->base));
|
|
cmdq_mbox_destroy(mtk_crtc->cmdq_client);
|
|
mtk_crtc->cmdq_client = NULL;
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|