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d57eb825e0
Add support for GPIO controller from RDA Micro. This GPIO controller is an in house IP, developed by RDA Micro (now Unisoc) for the use in RDA88* series of SoCs. There are multiple GPIO ports present in all SoCs, each capable of addressing 32 GPIOs. But only first 8 pins have the interrupt capability. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20191021064413.19840-4-manivannan.sadhasivam@linaro.org Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
295 lines
7.7 KiB
C
295 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* RDA Micro GPIO driver
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*
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* Copyright (C) 2012 RDA Micro Inc.
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* Copyright (C) 2019 Manivannan Sadhasivam
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*/
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define RDA_GPIO_OEN_VAL 0x00
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#define RDA_GPIO_OEN_SET_OUT 0x04
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#define RDA_GPIO_OEN_SET_IN 0x08
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#define RDA_GPIO_VAL 0x0c
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#define RDA_GPIO_SET 0x10
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#define RDA_GPIO_CLR 0x14
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#define RDA_GPIO_INT_CTRL_SET 0x18
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#define RDA_GPIO_INT_CTRL_CLR 0x1c
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#define RDA_GPIO_INT_CLR 0x20
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#define RDA_GPIO_INT_STATUS 0x24
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#define RDA_GPIO_IRQ_RISE_SHIFT 0
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#define RDA_GPIO_IRQ_FALL_SHIFT 8
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#define RDA_GPIO_DEBOUCE_SHIFT 16
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#define RDA_GPIO_LEVEL_SHIFT 24
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#define RDA_GPIO_IRQ_MASK 0xff
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/* Each bank consists of 32 GPIOs */
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#define RDA_GPIO_BANK_NR 32
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struct rda_gpio {
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struct gpio_chip chip;
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void __iomem *base;
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spinlock_t lock;
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struct irq_chip irq_chip;
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int irq;
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};
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static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset,
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u16 reg, int val)
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{
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struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
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void __iomem *base = rda_gpio->base;
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unsigned long flags;
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u32 tmp;
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spin_lock_irqsave(&rda_gpio->lock, flags);
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tmp = readl_relaxed(base + reg);
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if (val)
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tmp |= BIT(offset);
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else
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tmp &= ~BIT(offset);
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writel_relaxed(tmp, base + reg);
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spin_unlock_irqrestore(&rda_gpio->lock, flags);
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}
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static void rda_gpio_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
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void __iomem *base = rda_gpio->base;
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u32 offset = irqd_to_hwirq(data);
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u32 value;
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value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
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value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
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}
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static void rda_gpio_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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u32 offset = irqd_to_hwirq(data);
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rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1);
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}
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static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset,
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unsigned int flow_type)
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{
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struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
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void __iomem *base = rda_gpio->base;
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u32 value;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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/* Set rising edge trigger */
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value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
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/* Switch to edge trigger interrupt */
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value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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/* Set falling edge trigger */
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value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
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/* Switch to edge trigger interrupt */
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value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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/* Set both edge trigger */
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value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
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value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
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/* Switch to edge trigger interrupt */
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value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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/* Set high level trigger */
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value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
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/* Switch to level trigger interrupt */
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value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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/* Set low level trigger */
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value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
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/* Switch to level trigger interrupt */
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value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
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writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void rda_gpio_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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u32 offset = irqd_to_hwirq(data);
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u32 trigger = irqd_get_trigger_type(data);
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rda_gpio_set_irq(chip, offset, trigger);
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}
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static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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u32 offset = irqd_to_hwirq(data);
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int ret;
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ret = rda_gpio_set_irq(chip, offset, flow_type);
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if (ret)
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return ret;
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(data, handle_level_irq);
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else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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irq_set_handler_locked(data, handle_edge_irq);
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return 0;
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}
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static void rda_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *ic = irq_desc_get_chip(desc);
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struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
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unsigned long status;
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u32 n, girq;
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chained_irq_enter(ic, desc);
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status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS);
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/* Only lower 8 bits are capable of generating interrupts */
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status &= RDA_GPIO_IRQ_MASK;
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for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) {
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girq = irq_find_mapping(chip->irq.domain, n);
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generic_handle_irq(girq);
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}
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chained_irq_exit(ic, desc);
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}
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static int rda_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct gpio_irq_chip *girq;
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struct rda_gpio *rda_gpio;
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u32 ngpios;
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int ret;
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rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL);
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if (!rda_gpio)
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return -ENOMEM;
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ret = device_property_read_u32(dev, "ngpios", &ngpios);
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if (ret < 0)
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return ret;
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/*
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* Not all ports have interrupt capability. For instance, on
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* RDA8810PL, GPIOC doesn't support interrupt. So we must handle
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* those also.
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*/
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rda_gpio->irq = platform_get_irq(pdev, 0);
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rda_gpio->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rda_gpio->base))
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return PTR_ERR(rda_gpio->base);
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spin_lock_init(&rda_gpio->lock);
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ret = bgpio_init(&rda_gpio->chip, dev, 4,
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rda_gpio->base + RDA_GPIO_VAL,
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rda_gpio->base + RDA_GPIO_SET,
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rda_gpio->base + RDA_GPIO_CLR,
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rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
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rda_gpio->base + RDA_GPIO_OEN_SET_IN,
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BGPIOF_READ_OUTPUT_REG_SET);
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if (ret) {
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dev_err(dev, "bgpio_init failed\n");
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return ret;
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}
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rda_gpio->chip.label = dev_name(dev);
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rda_gpio->chip.ngpio = ngpios;
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rda_gpio->chip.base = -1;
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rda_gpio->chip.parent = dev;
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rda_gpio->chip.of_node = np;
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if (rda_gpio->irq >= 0) {
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rda_gpio->irq_chip.name = "rda-gpio",
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rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack,
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rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask,
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rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask,
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rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type,
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rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE,
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girq = &rda_gpio->chip.irq;
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girq->chip = &rda_gpio->irq_chip;
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girq->handler = handle_bad_irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->parent_handler = rda_gpio_irq_handler;
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girq->parent_handler_data = rda_gpio;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = rda_gpio->irq;
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}
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platform_set_drvdata(pdev, rda_gpio);
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return devm_gpiochip_add_data(dev, &rda_gpio->chip, rda_gpio);
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}
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static const struct of_device_id rda_gpio_of_match[] = {
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{ .compatible = "rda,8810pl-gpio", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rda_gpio_of_match);
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static struct platform_driver rda_gpio_driver = {
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.probe = rda_gpio_probe,
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.driver = {
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.name = "rda-gpio",
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.of_match_table = rda_gpio_of_match,
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},
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};
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module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe);
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MODULE_DESCRIPTION("RDA Micro GPIO driver");
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MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
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MODULE_LICENSE("GPL v2");
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