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0f2c7af45d
Since 5.10-rc1 i.MX is a devicetree-only platform, so simplify the code by removing the unused non-DT support. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20201117105917.27591-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
555 lines
14 KiB
C
555 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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//
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// Based on code from Freescale Semiconductor,
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// Authors: Daniel Mack, Juergen Beisert.
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// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/gpio/driver.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/bug.h>
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/* device type dependent stuff */
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struct mxc_gpio_hwdata {
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unsigned dr_reg;
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unsigned gdir_reg;
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unsigned psr_reg;
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unsigned icr1_reg;
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unsigned icr2_reg;
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unsigned imr_reg;
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unsigned isr_reg;
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int edge_sel_reg;
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unsigned low_level;
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unsigned high_level;
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unsigned rise_edge;
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unsigned fall_edge;
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};
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struct mxc_gpio_reg_saved {
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u32 icr1;
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u32 icr2;
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u32 imr;
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u32 gdir;
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u32 edge_sel;
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u32 dr;
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};
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struct mxc_gpio_port {
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struct list_head node;
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void __iomem *base;
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struct clk *clk;
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int irq;
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int irq_high;
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struct irq_domain *domain;
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struct gpio_chip gc;
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struct device *dev;
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u32 both_edges;
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struct mxc_gpio_reg_saved gpio_saved_reg;
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bool power_off;
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const struct mxc_gpio_hwdata *hwdata;
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};
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static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
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.dr_reg = 0x1c,
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.gdir_reg = 0x00,
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.psr_reg = 0x24,
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.icr1_reg = 0x28,
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.icr2_reg = 0x2c,
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.imr_reg = 0x30,
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.isr_reg = 0x34,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x03,
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.high_level = 0x02,
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.rise_edge = 0x00,
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.fall_edge = 0x01,
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};
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static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = -EINVAL,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
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.dr_reg = 0x00,
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.gdir_reg = 0x04,
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.psr_reg = 0x08,
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.icr1_reg = 0x0c,
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.icr2_reg = 0x10,
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.imr_reg = 0x14,
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.isr_reg = 0x18,
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.edge_sel_reg = 0x1c,
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.low_level = 0x00,
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.high_level = 0x01,
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.rise_edge = 0x02,
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.fall_edge = 0x03,
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};
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#define GPIO_DR (port->hwdata->dr_reg)
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#define GPIO_GDIR (port->hwdata->gdir_reg)
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#define GPIO_PSR (port->hwdata->psr_reg)
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#define GPIO_ICR1 (port->hwdata->icr1_reg)
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#define GPIO_ICR2 (port->hwdata->icr2_reg)
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#define GPIO_IMR (port->hwdata->imr_reg)
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#define GPIO_ISR (port->hwdata->isr_reg)
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#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
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#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
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#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
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#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
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#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
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#define GPIO_INT_BOTH_EDGES 0x4
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static const struct of_device_id mxc_gpio_dt_ids[] = {
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{ .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
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{ .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
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{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
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{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
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{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
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/*
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* MX2 has one interrupt *for all* gpio ports. The list is used
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* to save the references to all ports, so that mx2_gpio_irq_handler
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* can walk through all interrupt status registers.
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*/
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static LIST_HEAD(mxc_gpio_ports);
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static int gpio_set_irq_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 bit, val;
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u32 gpio_idx = d->hwirq;
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int edge;
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void __iomem *reg = port->base;
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port->both_edges &= ~(1 << gpio_idx);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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if (GPIO_EDGE_SEL >= 0) {
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edge = GPIO_INT_BOTH_EDGES;
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} else {
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val = port->gc.get(&port->gc, gpio_idx);
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if (val) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
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} else {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
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}
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port->both_edges |= 1 << gpio_idx;
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}
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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if (GPIO_EDGE_SEL >= 0) {
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val = readl(port->base + GPIO_EDGE_SEL);
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if (edge == GPIO_INT_BOTH_EDGES)
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writel(val | (1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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else
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writel(val & ~(1 << gpio_idx),
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port->base + GPIO_EDGE_SEL);
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}
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if (edge != GPIO_INT_BOTH_EDGES) {
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reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
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bit = gpio_idx & 0xf;
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val = readl(reg) & ~(0x3 << (bit << 1));
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writel(val | (edge << (bit << 1)), reg);
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}
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writel(1 << gpio_idx, port->base + GPIO_ISR);
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return 0;
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}
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static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
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{
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void __iomem *reg = port->base;
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u32 bit, val;
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int edge;
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reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
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bit = gpio & 0xf;
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val = readl(reg);
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edge = (val >> (bit << 1)) & 3;
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val &= ~(0x3 << (bit << 1));
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if (edge == GPIO_INT_HIGH_LEV) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
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} else if (edge == GPIO_INT_LOW_LEV) {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
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} else {
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pr_err("mxc: invalid configuration for GPIO %d: %x\n",
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gpio, edge);
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return;
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}
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writel(val | (edge << (bit << 1)), reg);
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}
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/* handle 32 interrupts in one status register */
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static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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{
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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if (port->both_edges & (1 << irqoffset))
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mxc_flip_edge(port, irqoffset);
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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}
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/* MX1 and MX3 has one interrupt *per* gpio port */
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static void mx3_gpio_irq_handler(struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
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mxc_gpio_irq_handler(port, irq_stat);
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chained_irq_exit(chip, desc);
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}
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/* MX2 has one interrupt *for all* gpio ports */
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static void mx2_gpio_irq_handler(struct irq_desc *desc)
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{
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u32 irq_msk, irq_stat;
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struct mxc_gpio_port *port;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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/* walk through all interrupt status registers */
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list_for_each_entry(port, &mxc_gpio_ports, node) {
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irq_msk = readl(port->base + GPIO_IMR);
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if (!irq_msk)
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continue;
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irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
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if (irq_stat)
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mxc_gpio_irq_handler(port, irq_stat);
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}
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chained_irq_exit(chip, desc);
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}
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/*
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* Set interrupt number "irq" in the GPIO as a wake-up source.
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* While system is running, all registered GPIO interrupts need to have
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* wake-up enabled. When system is suspended, only selected GPIO interrupts
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* need to have wake-up enabled.
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* @param irq interrupt source number
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* @param enable enable as wake-up if equal to non-zero
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* @return This function returns 0 on success.
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*/
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static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxc_gpio_port *port = gc->private;
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u32 gpio_idx = d->hwirq;
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int ret;
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if (enable) {
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if (port->irq_high && (gpio_idx >= 16))
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ret = enable_irq_wake(port->irq_high);
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else
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ret = enable_irq_wake(port->irq);
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} else {
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if (port->irq_high && (gpio_idx >= 16))
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ret = disable_irq_wake(port->irq_high);
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else
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ret = disable_irq_wake(port->irq);
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}
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return ret;
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}
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static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int rv;
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gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
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port->base, handle_level_irq);
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if (!gc)
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return -ENOMEM;
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gc->private = port;
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_set_irq_type;
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ct->chip.irq_set_wake = gpio_set_wake_irq;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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ct->regs.ack = GPIO_ISR;
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ct->regs.mask = GPIO_IMR;
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rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
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IRQ_GC_INIT_NESTED_LOCK,
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IRQ_NOREQUEST, 0);
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return rv;
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}
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static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct mxc_gpio_port *port = gpiochip_get_data(gc);
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return irq_find_mapping(port->domain, offset);
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}
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static int mxc_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mxc_gpio_port *port;
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int irq_count;
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int irq_base;
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int err;
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port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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port->dev = &pdev->dev;
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port->hwdata = device_get_match_data(&pdev->dev);
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port->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(port->base))
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return PTR_ERR(port->base);
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irq_count = platform_irq_count(pdev);
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if (irq_count < 0)
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return irq_count;
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if (irq_count > 1) {
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port->irq_high = platform_get_irq(pdev, 1);
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if (port->irq_high < 0)
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port->irq_high = 0;
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}
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port->irq = platform_get_irq(pdev, 0);
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if (port->irq < 0)
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return port->irq;
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/* the controller clock is optional */
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port->clk = devm_clk_get_optional(&pdev->dev, NULL);
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if (IS_ERR(port->clk))
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return PTR_ERR(port->clk);
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err = clk_prepare_enable(port->clk);
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if (err) {
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dev_err(&pdev->dev, "Unable to enable clock.\n");
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return err;
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}
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if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
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port->power_off = true;
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/* disable the interrupt and clear the status */
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writel(0, port->base + GPIO_IMR);
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writel(~0, port->base + GPIO_ISR);
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if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
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/*
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* Setup one handler for all GPIO interrupts. Actually setting
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* the handler is needed only once, but doing it for every port
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* is more robust and easier.
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*/
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irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
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} else {
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/* setup one handler for each entry */
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irq_set_chained_handler_and_data(port->irq,
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mx3_gpio_irq_handler, port);
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if (port->irq_high > 0)
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/* setup handler for GPIO 16 to 31 */
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irq_set_chained_handler_and_data(port->irq_high,
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mx3_gpio_irq_handler,
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port);
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}
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err = bgpio_init(&port->gc, &pdev->dev, 4,
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port->base + GPIO_PSR,
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port->base + GPIO_DR, NULL,
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port->base + GPIO_GDIR, NULL,
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BGPIOF_READ_OUTPUT_REG_SET);
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if (err)
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goto out_bgio;
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port->gc.request = gpiochip_generic_request;
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port->gc.free = gpiochip_generic_free;
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port->gc.to_irq = mxc_gpio_to_irq;
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port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
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pdev->id * 32;
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err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
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if (err)
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goto out_bgio;
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irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
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if (irq_base < 0) {
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err = irq_base;
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goto out_bgio;
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}
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port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!port->domain) {
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err = -ENODEV;
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goto out_bgio;
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}
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/* gpio-mxc can be a generic irq chip */
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err = mxc_gpio_init_gc(port, irq_base);
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if (err < 0)
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goto out_irqdomain_remove;
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list_add_tail(&port->node, &mxc_gpio_ports);
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platform_set_drvdata(pdev, port);
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return 0;
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out_irqdomain_remove:
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irq_domain_remove(port->domain);
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out_bgio:
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clk_disable_unprepare(port->clk);
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dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
|
|
return err;
|
|
}
|
|
|
|
static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
|
|
{
|
|
if (!port->power_off)
|
|
return;
|
|
|
|
port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
|
|
port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
|
|
port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
|
|
port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
|
|
port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
|
|
port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
|
|
}
|
|
|
|
static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
|
|
{
|
|
if (!port->power_off)
|
|
return;
|
|
|
|
writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
|
|
writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
|
|
writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
|
|
writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
|
|
writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
|
|
writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
|
|
}
|
|
|
|
static int mxc_gpio_syscore_suspend(void)
|
|
{
|
|
struct mxc_gpio_port *port;
|
|
|
|
/* walk through all ports */
|
|
list_for_each_entry(port, &mxc_gpio_ports, node) {
|
|
mxc_gpio_save_regs(port);
|
|
clk_disable_unprepare(port->clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mxc_gpio_syscore_resume(void)
|
|
{
|
|
struct mxc_gpio_port *port;
|
|
int ret;
|
|
|
|
/* walk through all ports */
|
|
list_for_each_entry(port, &mxc_gpio_ports, node) {
|
|
ret = clk_prepare_enable(port->clk);
|
|
if (ret) {
|
|
pr_err("mxc: failed to enable gpio clock %d\n", ret);
|
|
return;
|
|
}
|
|
mxc_gpio_restore_regs(port);
|
|
}
|
|
}
|
|
|
|
static struct syscore_ops mxc_gpio_syscore_ops = {
|
|
.suspend = mxc_gpio_syscore_suspend,
|
|
.resume = mxc_gpio_syscore_resume,
|
|
};
|
|
|
|
static struct platform_driver mxc_gpio_driver = {
|
|
.driver = {
|
|
.name = "gpio-mxc",
|
|
.of_match_table = mxc_gpio_dt_ids,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = mxc_gpio_probe,
|
|
};
|
|
|
|
static int __init gpio_mxc_init(void)
|
|
{
|
|
register_syscore_ops(&mxc_gpio_syscore_ops);
|
|
|
|
return platform_driver_register(&mxc_gpio_driver);
|
|
}
|
|
subsys_initcall(gpio_mxc_init);
|
|
|
|
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
|
|
MODULE_DESCRIPTION("i.MX GPIO Driver");
|
|
MODULE_LICENSE("GPL");
|