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1c12857c67
Fix a spelling typo in gpio-ftgpio010.c by codespell s/desireable/desirable/ Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Link: https://lore.kernel.org/r/20200424154103.10311-2-zhengdejin5@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
355 lines
8.8 KiB
C
355 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Faraday Technolog FTGPIO010 gpiochip and interrupt routines
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Based on arch/arm/mach-gemini/gpio.c:
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on plat-mxc/gpio.c:
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*/
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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/* GPIO registers definition */
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#define GPIO_DATA_OUT 0x00
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#define GPIO_DATA_IN 0x04
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#define GPIO_DIR 0x08
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#define GPIO_BYPASS_IN 0x0C
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#define GPIO_DATA_SET 0x10
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#define GPIO_DATA_CLR 0x14
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#define GPIO_PULL_EN 0x18
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#define GPIO_PULL_TYPE 0x1C
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#define GPIO_INT_EN 0x20
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#define GPIO_INT_STAT_RAW 0x24
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#define GPIO_INT_STAT_MASKED 0x28
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#define GPIO_INT_MASK 0x2C
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#define GPIO_INT_CLR 0x30
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#define GPIO_INT_TYPE 0x34
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#define GPIO_INT_BOTH_EDGE 0x38
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#define GPIO_INT_LEVEL 0x3C
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#define GPIO_DEBOUNCE_EN 0x40
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#define GPIO_DEBOUNCE_PRESCALE 0x44
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/**
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* struct ftgpio_gpio - Gemini GPIO state container
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* @dev: containing device for this instance
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* @gc: gpiochip for this instance
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* @irq: irqchip for this instance
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* @base: remapped I/O-memory base
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* @clk: silicon clock
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*/
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struct ftgpio_gpio {
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struct device *dev;
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struct gpio_chip gc;
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struct irq_chip irq;
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void __iomem *base;
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struct clk *clk;
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};
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static void ftgpio_gpio_ack_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
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}
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static void ftgpio_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 val;
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val = readl(g->base + GPIO_INT_EN);
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val &= ~BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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}
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static void ftgpio_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 val;
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val = readl(g->base + GPIO_INT_EN);
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val |= BIT(irqd_to_hwirq(d));
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writel(val, g->base + GPIO_INT_EN);
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}
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static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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u32 mask = BIT(irqd_to_hwirq(d));
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u32 reg_both, reg_level, reg_type;
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reg_type = readl(g->base + GPIO_INT_TYPE);
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reg_level = readl(g->base + GPIO_INT_LEVEL);
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reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(d, handle_edge_irq);
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reg_type &= ~mask;
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reg_both &= ~mask;
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reg_level |= mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(d, handle_level_irq);
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reg_type |= mask;
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reg_level |= mask;
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break;
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default:
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irq_set_handler_locked(d, handle_bad_irq);
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return -EINVAL;
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}
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writel(reg_type, g->base + GPIO_INT_TYPE);
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writel(reg_level, g->base + GPIO_INT_LEVEL);
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writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
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ftgpio_gpio_ack_irq(d);
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return 0;
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}
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static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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int offset;
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unsigned long stat;
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chained_irq_enter(irqchip, desc);
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stat = readl(g->base + GPIO_INT_STAT_RAW);
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if (stat)
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for_each_set_bit(offset, &stat, gc->ngpio)
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generic_handle_irq(irq_find_mapping(gc->irq.domain,
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offset));
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chained_irq_exit(irqchip, desc);
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}
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static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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enum pin_config_param param = pinconf_to_config_param(config);
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u32 arg = pinconf_to_config_argument(config);
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struct ftgpio_gpio *g = gpiochip_get_data(gc);
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unsigned long pclk_freq;
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u32 deb_div;
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u32 val;
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if (param != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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/*
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* Debounce only works if interrupts are enabled. The manual
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* states that if PCLK is 66 MHz, and this is set to 0x7D0, then
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* PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
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* 2000 decimal, so what they mean is simply that the PCLK is
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* divided by this value.
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*
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* As we get a debounce setting in microseconds, we calculate the
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* desired period time and see if we can get a suitable debounce
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* time.
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*/
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pclk_freq = clk_get_rate(g->clk);
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deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
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/* This register is only 24 bits wide */
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if (deb_div > (1 << 24))
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return -ENOTSUPP;
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dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
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deb_div, (pclk_freq/deb_div));
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val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
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if (val == deb_div) {
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/*
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* The debounce timer happens to already be set to the
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* desirable value, what a coincidence! We can just enable
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* debounce on this GPIO line and return. This happens more
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* often than you think, for example when all GPIO keys
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* on a system are requesting the same debounce interval.
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*/
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val = readl(g->base + GPIO_DEBOUNCE_EN);
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val |= BIT(offset);
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writel(val, g->base + GPIO_DEBOUNCE_EN);
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return 0;
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}
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val = readl(g->base + GPIO_DEBOUNCE_EN);
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if (val) {
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/*
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* Oh no! Someone is already using the debounce with
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* another setting than what we need. Bummer.
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*/
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return -ENOTSUPP;
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}
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/* First come, first serve */
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writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
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/* Enable debounce */
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val |= BIT(offset);
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writel(val, g->base + GPIO_DEBOUNCE_EN);
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return 0;
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}
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static int ftgpio_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ftgpio_gpio *g;
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struct gpio_irq_chip *girq;
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int irq;
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int ret;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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if (!g)
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return -ENOMEM;
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g->dev = dev;
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g->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(g->base))
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return PTR_ERR(g->base);
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return irq ? irq : -EINVAL;
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g->clk = devm_clk_get(dev, NULL);
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if (!IS_ERR(g->clk)) {
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ret = clk_prepare_enable(g->clk);
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if (ret)
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return ret;
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} else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
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/*
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* Percolate deferrals, for anything else,
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* just live without the clocking.
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*/
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return PTR_ERR(g->clk);
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}
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ret = bgpio_init(&g->gc, dev, 4,
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g->base + GPIO_DATA_IN,
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g->base + GPIO_DATA_SET,
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g->base + GPIO_DATA_CLR,
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g->base + GPIO_DIR,
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NULL,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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goto dis_clk;
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}
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g->gc.label = "FTGPIO010";
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g->gc.base = -1;
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g->gc.parent = dev;
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g->gc.owner = THIS_MODULE;
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/* ngpio is set by bgpio_init() */
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/* We need a silicon clock to do debounce */
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if (!IS_ERR(g->clk))
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g->gc.set_config = ftgpio_gpio_set_config;
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g->irq.name = "FTGPIO010";
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g->irq.irq_ack = ftgpio_gpio_ack_irq;
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g->irq.irq_mask = ftgpio_gpio_mask_irq;
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g->irq.irq_unmask = ftgpio_gpio_unmask_irq;
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g->irq.irq_set_type = ftgpio_gpio_set_irq_type;
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girq = &g->gc.irq;
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girq->chip = &g->irq;
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girq->parent_handler = ftgpio_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents) {
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ret = -ENOMEM;
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goto dis_clk;
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}
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_bad_irq;
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girq->parents[0] = irq;
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/* Disable, unmask and clear all interrupts */
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writel(0x0, g->base + GPIO_INT_EN);
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writel(0x0, g->base + GPIO_INT_MASK);
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writel(~0x0, g->base + GPIO_INT_CLR);
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/* Clear any use of debounce */
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writel(0x0, g->base + GPIO_DEBOUNCE_EN);
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ret = devm_gpiochip_add_data(dev, &g->gc, g);
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if (ret)
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goto dis_clk;
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platform_set_drvdata(pdev, g);
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dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
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return 0;
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dis_clk:
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if (!IS_ERR(g->clk))
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clk_disable_unprepare(g->clk);
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return ret;
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}
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static int ftgpio_gpio_remove(struct platform_device *pdev)
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{
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struct ftgpio_gpio *g = platform_get_drvdata(pdev);
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if (!IS_ERR(g->clk))
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clk_disable_unprepare(g->clk);
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return 0;
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}
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static const struct of_device_id ftgpio_gpio_of_match[] = {
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{
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.compatible = "cortina,gemini-gpio",
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},
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{
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.compatible = "moxa,moxart-gpio",
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},
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{
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.compatible = "faraday,ftgpio010",
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},
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{},
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};
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static struct platform_driver ftgpio_gpio_driver = {
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.driver = {
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.name = "ftgpio010-gpio",
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.of_match_table = of_match_ptr(ftgpio_gpio_of_match),
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},
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.probe = ftgpio_gpio_probe,
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.remove = ftgpio_gpio_remove,
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};
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builtin_platform_driver(ftgpio_gpio_driver);
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