linux/drivers/cxl
Dave Jiang 863027d409 cxl: Split out host bridge access coordinates
The difference between access class 0 and access class 1 for 'struct
access_coordinate', if any, is that class 0 is for the distance from
the target to the closest initiator and that class 1 is for the distance
from the target to the closest CPU. For CXL memory, the nearest initiator
may not necessarily be a CPU node. The performance path from the CXL
endpoint to the host bridge should remain the same. However, the numbers
extracted and stored from HMAT is the difference for the two access
classes. Split out the performance numbers for the host bridge (generic
target) from the calculation of the entire path in order to allow
calculation of both access classes for a CXL region.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20240308220055.2172956-7-dave.jiang@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2024-03-12 12:34:11 -07:00
..
core cxl: Split out host bridge access coordinates 2024-03-12 12:34:11 -07:00
acpi.c ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes 2024-03-12 12:34:11 -07:00
cxl.h cxl: Split out host bridge access coordinates 2024-03-12 12:34:11 -07:00
cxlmem.h cxl: Change 'struct cxl_memdev_state' *_perf_list to single 'struct cxl_dpa_perf' 2024-02-16 23:20:34 -08:00
cxlpci.h cxl: Calculate and store PCI link latency for the downstream ports 2023-12-22 14:53:49 -08:00
Kconfig cxl: Add callback to parse the DSMAS subtables from CDAT 2023-12-22 14:33:10 -08:00
Makefile cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation 2022-11-30 16:30:47 -08:00
mem.c cxl: Fix sysfs export of qos_class for memdev 2024-02-16 23:20:34 -08:00
pci.c acpi/ghes: Remove CXL CPER notifications 2024-02-20 22:50:52 -08:00
pmem.c cxl/mbox: Move mailbox related driver state to its own data structure 2023-06-25 14:31:08 -07:00
pmu.h cxl/pci: Find and register CXL PMU devices 2023-05-30 11:20:35 -07:00
port.c cxl: Refactor to use __free() for cxl_root allocation in cxl_endpoint_port_probe() 2024-01-05 14:36:29 -08:00
security.c Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl 2023-06-25 17:16:51 -07:00