Conor Dooley b60cf8e59e dt-bindings: riscv: fix SiFive l2-cache's cache-sets ... Fix device tree schema validation error messages for the SiFive Unmatched: ' cache-sets:0:0: 1024 was expected'. The existing bindings allow for just 1024 cache-sets but the fu740 on Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary power of two, however this is not supported by dt-schema. The RTL for the IP, to which the number of cache-sets is a tunable parameter, has been released publicly so speculatively adding a small number of "reasonable" values seems unwise also. Instead, as the binding only supports two distinct controllers: add 2048 and explicitly lock it to the fu740's l2 cache while limiting 1024 to the l2 cache on the fu540. Fixes: af951c3a11 ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740") Reported-by: Atul Khare <atulkhare@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220803185359.942928-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-08-11 14:00:11 -07:00
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canaan.yaml	dt-bindings: add Canaan boards compatible strings	2021-02-22 17:51:06 -08:00
cpus.yaml	dt-bindings: riscv: document cbom-block-size	2022-07-28 15:30:21 -07:00
microchip.yaml	dt-bindings: riscv: microchip: add polarberry compatible string	2022-06-01 15:28:23 -07:00
sifive-l2-cache.yaml	dt-bindings: riscv: fix SiFive l2-cache's cache-sets	2022-08-11 14:00:11 -07:00
sifive.yaml	dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board	2021-01-07 17:37:41 -08:00
starfive.yaml	dt-bindings: riscv: add starfive jh7100 bindings	2021-08-04 13:25:28 -07:00