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85ce928dbb
- Avoid the use of hardware defined structure bfi_sge_s for DMA requests in host. - Defined a generic address len pair to represent a DMA memory chunk (bfi_alen_s). Signed-off-by: Krishna Gudipati <kgudipat@brocade.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
454 lines
14 KiB
C
454 lines
14 KiB
C
/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __BFA_IOC_H__
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#define __BFA_IOC_H__
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#include "bfad_drv.h"
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#include "bfa_cs.h"
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#include "bfi.h"
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#define BFA_DBG_FWTRC_ENTS (BFI_IOC_TRC_ENTS)
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#define BFA_DBG_FWTRC_LEN \
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(BFA_DBG_FWTRC_ENTS * sizeof(struct bfa_trc_s) + \
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(sizeof(struct bfa_trc_mod_s) - \
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BFA_TRC_MAX * sizeof(struct bfa_trc_s)))
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/*
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* BFA timer declarations
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*/
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typedef void (*bfa_timer_cbfn_t)(void *);
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/*
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* BFA timer data structure
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*/
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struct bfa_timer_s {
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struct list_head qe;
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bfa_timer_cbfn_t timercb;
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void *arg;
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int timeout; /* in millisecs */
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};
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/*
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* Timer module structure
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*/
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struct bfa_timer_mod_s {
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struct list_head timer_q;
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};
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#define BFA_TIMER_FREQ 200 /* specified in millisecs */
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void bfa_timer_beat(struct bfa_timer_mod_s *mod);
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void bfa_timer_begin(struct bfa_timer_mod_s *mod, struct bfa_timer_s *timer,
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bfa_timer_cbfn_t timercb, void *arg,
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unsigned int timeout);
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void bfa_timer_stop(struct bfa_timer_s *timer);
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/*
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* Generic Scatter Gather Element used by driver
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*/
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struct bfa_sge_s {
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u32 sg_len;
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void *sg_addr;
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};
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#define bfa_sge_word_swap(__sge) do { \
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((u32 *)(__sge))[0] = swab32(((u32 *)(__sge))[0]); \
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((u32 *)(__sge))[1] = swab32(((u32 *)(__sge))[1]); \
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((u32 *)(__sge))[2] = swab32(((u32 *)(__sge))[2]); \
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} while (0)
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#define bfa_swap_words(_x) ( \
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((_x) << 32) | ((_x) >> 32))
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#ifdef __BIG_ENDIAN
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#define bfa_sge_to_be(_x)
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#define bfa_sge_to_le(_x) bfa_sge_word_swap(_x)
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#define bfa_sgaddr_le(_x) bfa_swap_words(_x)
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#else
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#define bfa_sge_to_be(_x) bfa_sge_word_swap(_x)
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#define bfa_sge_to_le(_x)
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#define bfa_sgaddr_le(_x) (_x)
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#endif
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/*
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* PCI device information required by IOC
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*/
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struct bfa_pcidev_s {
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int pci_slot;
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u8 pci_func;
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u16 device_id;
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void __iomem *pci_bar_kva;
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};
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/*
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* Structure used to remember the DMA-able memory block's KVA and Physical
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* Address
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*/
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struct bfa_dma_s {
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void *kva; /* ! Kernel virtual address */
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u64 pa; /* ! Physical address */
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};
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#define BFA_DMA_ALIGN_SZ 256
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#define BFA_ROUNDUP(_l, _s) (((_l) + ((_s) - 1)) & ~((_s) - 1))
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/*
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* smem size for Crossbow and Catapult
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*/
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#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
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#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
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#define bfa_dma_be_addr_set(dma_addr, pa) \
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__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
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static inline void
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__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
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{
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dma_addr->a32.addr_lo = cpu_to_be32(pa);
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dma_addr->a32.addr_hi = cpu_to_be32(pa >> 32);
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}
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#define bfa_alen_set(__alen, __len, __pa) \
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__bfa_alen_set(__alen, __len, (u64)__pa)
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static inline void
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__bfa_alen_set(struct bfi_alen_s *alen, u32 len, u64 pa)
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{
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alen->al_len = cpu_to_be32(len);
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bfa_dma_be_addr_set(alen->al_addr, pa);
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}
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struct bfa_ioc_regs_s {
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void __iomem *hfn_mbox_cmd;
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void __iomem *hfn_mbox;
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void __iomem *lpu_mbox_cmd;
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void __iomem *lpu_mbox;
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void __iomem *pss_ctl_reg;
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void __iomem *pss_err_status_reg;
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void __iomem *app_pll_fast_ctl_reg;
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void __iomem *app_pll_slow_ctl_reg;
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void __iomem *ioc_sem_reg;
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void __iomem *ioc_usage_sem_reg;
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void __iomem *ioc_init_sem_reg;
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void __iomem *ioc_usage_reg;
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void __iomem *host_page_num_fn;
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void __iomem *heartbeat;
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void __iomem *ioc_fwstate;
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void __iomem *alt_ioc_fwstate;
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void __iomem *ll_halt;
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void __iomem *alt_ll_halt;
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void __iomem *err_set;
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void __iomem *ioc_fail_sync;
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void __iomem *shirq_isr_next;
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void __iomem *shirq_msk_next;
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void __iomem *smem_page_start;
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u32 smem_pg0;
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};
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#define bfa_mem_read(_raddr, _off) swab32(readl(((_raddr) + (_off))))
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#define bfa_mem_write(_raddr, _off, _val) \
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writel(swab32((_val)), ((_raddr) + (_off)))
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/*
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* IOC Mailbox structures
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*/
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struct bfa_mbox_cmd_s {
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struct list_head qe;
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u32 msg[BFI_IOC_MSGSZ];
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};
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/*
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* IOC mailbox module
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*/
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typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg_s *m);
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struct bfa_ioc_mbox_mod_s {
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struct list_head cmd_q; /* pending mbox queue */
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int nmclass; /* number of handlers */
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struct {
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bfa_ioc_mbox_mcfunc_t cbfn; /* message handlers */
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void *cbarg;
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} mbhdlr[BFI_MC_MAX];
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};
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/*
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* IOC callback function interfaces
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*/
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typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
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typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
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typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
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typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
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struct bfa_ioc_cbfn_s {
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bfa_ioc_enable_cbfn_t enable_cbfn;
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bfa_ioc_disable_cbfn_t disable_cbfn;
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bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
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bfa_ioc_reset_cbfn_t reset_cbfn;
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};
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/*
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* Heartbeat failure notification queue element.
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*/
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struct bfa_ioc_hbfail_notify_s {
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struct list_head qe;
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bfa_ioc_hbfail_cbfn_t cbfn;
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void *cbarg;
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};
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/*
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* Initialize a heartbeat failure notification structure
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*/
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#define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do { \
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(__notify)->cbfn = (__cbfn); \
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(__notify)->cbarg = (__cbarg); \
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} while (0)
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struct bfa_iocpf_s {
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bfa_fsm_t fsm;
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struct bfa_ioc_s *ioc;
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u32 retry_count;
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bfa_boolean_t auto_recover;
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};
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struct bfa_ioc_s {
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bfa_fsm_t fsm;
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struct bfa_s *bfa;
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struct bfa_pcidev_s pcidev;
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struct bfa_timer_mod_s *timer_mod;
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struct bfa_timer_s ioc_timer;
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struct bfa_timer_s sem_timer;
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struct bfa_timer_s hb_timer;
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u32 hb_count;
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struct list_head hb_notify_q;
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void *dbg_fwsave;
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int dbg_fwsave_len;
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bfa_boolean_t dbg_fwsave_once;
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enum bfi_mclass ioc_mc;
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struct bfa_ioc_regs_s ioc_regs;
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struct bfa_trc_mod_s *trcmod;
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struct bfa_ioc_drv_stats_s stats;
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bfa_boolean_t fcmode;
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bfa_boolean_t ctdev;
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bfa_boolean_t cna;
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bfa_boolean_t pllinit;
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bfa_boolean_t stats_busy; /* outstanding stats */
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u8 port_id;
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struct bfa_dma_s attr_dma;
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struct bfi_ioc_attr_s *attr;
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struct bfa_ioc_cbfn_s *cbfn;
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struct bfa_ioc_mbox_mod_s mbox_mod;
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struct bfa_ioc_hwif_s *ioc_hwif;
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struct bfa_iocpf_s iocpf;
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};
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struct bfa_ioc_hwif_s {
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bfa_status_t (*ioc_pll_init) (void __iomem *rb, bfa_boolean_t fcmode);
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bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc);
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void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc);
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void (*ioc_reg_init) (struct bfa_ioc_s *ioc);
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void (*ioc_map_port) (struct bfa_ioc_s *ioc);
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void (*ioc_isr_mode_set) (struct bfa_ioc_s *ioc,
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bfa_boolean_t msix);
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void (*ioc_notify_fail) (struct bfa_ioc_s *ioc);
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void (*ioc_ownership_reset) (struct bfa_ioc_s *ioc);
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bfa_boolean_t (*ioc_sync_start) (struct bfa_ioc_s *ioc);
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void (*ioc_sync_join) (struct bfa_ioc_s *ioc);
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void (*ioc_sync_leave) (struct bfa_ioc_s *ioc);
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void (*ioc_sync_ack) (struct bfa_ioc_s *ioc);
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bfa_boolean_t (*ioc_sync_complete) (struct bfa_ioc_s *ioc);
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};
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#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
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#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
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#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
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#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
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#define bfa_ioc_fetch_stats(__ioc, __stats) \
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(((__stats)->drv_stats) = (__ioc)->stats)
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#define bfa_ioc_clr_stats(__ioc) \
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memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
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#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
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#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
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#define bfa_ioc_speed_sup(__ioc) \
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BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
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#define bfa_ioc_get_nports(__ioc) \
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BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
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#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
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#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
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#define BFA_IOC_FWIMG_TYPE(__ioc) \
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(((__ioc)->ctdev) ? \
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(((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
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BFI_IMAGE_CB_FC)
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#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
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(((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
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#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
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#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
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#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
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/*
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* IOC mailbox interface
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*/
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void bfa_ioc_mbox_queue(struct bfa_ioc_s *ioc, struct bfa_mbox_cmd_s *cmd);
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void bfa_ioc_mbox_register(struct bfa_ioc_s *ioc,
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bfa_ioc_mbox_mcfunc_t *mcfuncs);
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void bfa_ioc_mbox_isr(struct bfa_ioc_s *ioc);
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void bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len);
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void bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg);
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void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
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bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
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/*
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* IOC interfaces
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*/
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#define bfa_ioc_pll_init_asic(__ioc) \
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((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
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(__ioc)->fcmode))
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bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc);
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bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
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bfa_boolean_t bfa_ioc_ct_pll_init_complete(void __iomem *rb);
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bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
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#define bfa_ioc_isr_mode_set(__ioc, __msix) \
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((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
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#define bfa_ioc_ownership_reset(__ioc) \
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((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
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void bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc);
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void bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc);
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void bfa_ioc_attach(struct bfa_ioc_s *ioc, void *bfa,
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struct bfa_ioc_cbfn_s *cbfn, struct bfa_timer_mod_s *timer_mod);
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void bfa_ioc_auto_recover(bfa_boolean_t auto_recover);
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void bfa_ioc_detach(struct bfa_ioc_s *ioc);
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void bfa_ioc_pci_init(struct bfa_ioc_s *ioc, struct bfa_pcidev_s *pcidev,
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enum bfi_mclass mc);
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void bfa_ioc_mem_claim(struct bfa_ioc_s *ioc, u8 *dm_kva, u64 dm_pa);
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void bfa_ioc_enable(struct bfa_ioc_s *ioc);
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void bfa_ioc_disable(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_intx_claim(struct bfa_ioc_s *ioc);
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void bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type,
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u32 boot_param);
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void bfa_ioc_isr(struct bfa_ioc_s *ioc, struct bfi_mbmsg_s *msg);
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void bfa_ioc_error_isr(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_is_operational(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_is_initialized(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_is_disabled(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_fw_mismatch(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc);
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void bfa_ioc_reset_fwstate(struct bfa_ioc_s *ioc);
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enum bfa_ioc_type_e bfa_ioc_get_type(struct bfa_ioc_s *ioc);
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void bfa_ioc_get_adapter_serial_num(struct bfa_ioc_s *ioc, char *serial_num);
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void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc_s *ioc, char *fw_ver);
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void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc_s *ioc, char *optrom_ver);
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void bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model);
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void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc_s *ioc,
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char *manufacturer);
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void bfa_ioc_get_pci_chip_rev(struct bfa_ioc_s *ioc, char *chip_rev);
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enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc_s *ioc);
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void bfa_ioc_get_attr(struct bfa_ioc_s *ioc, struct bfa_ioc_attr_s *ioc_attr);
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void bfa_ioc_get_adapter_attr(struct bfa_ioc_s *ioc,
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struct bfa_adapter_attr_s *ad_attr);
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void bfa_ioc_debug_memclaim(struct bfa_ioc_s *ioc, void *dbg_fwsave);
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bfa_status_t bfa_ioc_debug_fwsave(struct bfa_ioc_s *ioc, void *trcdata,
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int *trclen);
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bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata,
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int *trclen);
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bfa_status_t bfa_ioc_debug_fwcore(struct bfa_ioc_s *ioc, void *buf,
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u32 *offset, int *buflen);
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void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_sem_get(void __iomem *sem_reg);
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void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc,
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struct bfi_ioc_image_hdr_s *fwhdr);
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bfa_boolean_t bfa_ioc_fwver_cmp(struct bfa_ioc_s *ioc,
|
|
struct bfi_ioc_image_hdr_s *fwhdr);
|
|
bfa_status_t bfa_ioc_fw_stats_get(struct bfa_ioc_s *ioc, void *stats);
|
|
bfa_status_t bfa_ioc_fw_stats_clear(struct bfa_ioc_s *ioc);
|
|
|
|
/*
|
|
* bfa mfg wwn API functions
|
|
*/
|
|
mac_t bfa_ioc_get_mac(struct bfa_ioc_s *ioc);
|
|
mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc);
|
|
|
|
/*
|
|
* F/W Image Size & Chunk
|
|
*/
|
|
extern u32 bfi_image_ct_fc_size;
|
|
extern u32 bfi_image_ct_cna_size;
|
|
extern u32 bfi_image_cb_fc_size;
|
|
extern u32 *bfi_image_ct_fc;
|
|
extern u32 *bfi_image_ct_cna;
|
|
extern u32 *bfi_image_cb_fc;
|
|
|
|
static inline u32 *
|
|
bfi_image_ct_fc_get_chunk(u32 off)
|
|
{ return (u32 *)(bfi_image_ct_fc + off); }
|
|
|
|
static inline u32 *
|
|
bfi_image_ct_cna_get_chunk(u32 off)
|
|
{ return (u32 *)(bfi_image_ct_cna + off); }
|
|
|
|
static inline u32 *
|
|
bfi_image_cb_fc_get_chunk(u32 off)
|
|
{ return (u32 *)(bfi_image_cb_fc + off); }
|
|
|
|
static inline u32*
|
|
bfa_cb_image_get_chunk(int type, u32 off)
|
|
{
|
|
switch (type) {
|
|
case BFI_IMAGE_CT_FC:
|
|
return bfi_image_ct_fc_get_chunk(off); break;
|
|
case BFI_IMAGE_CT_CNA:
|
|
return bfi_image_ct_cna_get_chunk(off); break;
|
|
case BFI_IMAGE_CB_FC:
|
|
return bfi_image_cb_fc_get_chunk(off); break;
|
|
default: return NULL;
|
|
}
|
|
}
|
|
|
|
static inline u32
|
|
bfa_cb_image_get_size(int type)
|
|
{
|
|
switch (type) {
|
|
case BFI_IMAGE_CT_FC:
|
|
return bfi_image_ct_fc_size; break;
|
|
case BFI_IMAGE_CT_CNA:
|
|
return bfi_image_ct_cna_size; break;
|
|
case BFI_IMAGE_CB_FC:
|
|
return bfi_image_cb_fc_size; break;
|
|
default: return 0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* CNA TRCMOD declaration
|
|
*/
|
|
/*
|
|
* !!! Only append to the enums defined here to avoid any versioning
|
|
* !!! needed between trace utility and driver version
|
|
*/
|
|
enum {
|
|
BFA_TRC_CNA_PORT = 1,
|
|
BFA_TRC_CNA_IOC = 2,
|
|
BFA_TRC_CNA_IOC_CB = 3,
|
|
BFA_TRC_CNA_IOC_CT = 4,
|
|
};
|
|
|
|
#endif /* __BFA_IOC_H__ */
|