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Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
295 lines
10 KiB
C
295 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
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#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11
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#define BLSP1_UART1_APPS_CLK_SRC 12
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#define BLSP1_UART2_APPS_CLK_SRC 13
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#define BLSP1_UART3_APPS_CLK_SRC 14
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22
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#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23
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#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24
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#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25
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#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26
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#define BLSP2_UART1_APPS_CLK_SRC 27
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#define BLSP2_UART2_APPS_CLK_SRC 28
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#define BLSP2_UART3_APPS_CLK_SRC 29
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#define GCC_AGGRE1_NOC_XO_CLK 30
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#define GCC_AGGRE1_UFS_AXI_CLK 31
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#define GCC_AGGRE1_USB3_AXI_CLK 32
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#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33
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#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34
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#define GCC_BIMC_HMSS_AXI_CLK 35
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#define GCC_BIMC_MSS_Q6_AXI_CLK 36
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#define GCC_BLSP1_AHB_CLK 37
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49
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#define GCC_BLSP1_SLEEP_CLK 50
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#define GCC_BLSP1_UART1_APPS_CLK 51
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#define GCC_BLSP1_UART2_APPS_CLK 52
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#define GCC_BLSP1_UART3_APPS_CLK 53
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#define GCC_BLSP2_AHB_CLK 54
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62
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#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63
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#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64
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#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65
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#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66
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#define GCC_BLSP2_SLEEP_CLK 67
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#define GCC_BLSP2_UART1_APPS_CLK 68
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#define GCC_BLSP2_UART2_APPS_CLK 69
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#define GCC_BLSP2_UART3_APPS_CLK 70
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#define GCC_CFG_NOC_USB3_AXI_CLK 71
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#define GCC_GP1_CLK 72
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#define GCC_GP2_CLK 73
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#define GCC_GP3_CLK 74
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#define GCC_GPU_BIMC_GFX_CLK 75
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#define GCC_GPU_BIMC_GFX_SRC_CLK 76
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#define GCC_GPU_CFG_AHB_CLK 77
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#define GCC_GPU_SNOC_DVM_GFX_CLK 78
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#define GCC_HMSS_AHB_CLK 79
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#define GCC_HMSS_AT_CLK 80
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#define GCC_HMSS_DVM_BUS_CLK 81
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#define GCC_HMSS_RBCPR_CLK 82
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#define GCC_HMSS_TRIG_CLK 83
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#define GCC_LPASS_AT_CLK 84
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#define GCC_LPASS_TRIG_CLK 85
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#define GCC_MMSS_NOC_CFG_AHB_CLK 86
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#define GCC_MMSS_QM_AHB_CLK 87
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#define GCC_MMSS_QM_CORE_CLK 88
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#define GCC_MMSS_SYS_NOC_AXI_CLK 89
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#define GCC_MSS_AT_CLK 90
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#define GCC_PCIE_0_AUX_CLK 91
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#define GCC_PCIE_0_CFG_AHB_CLK 92
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#define GCC_PCIE_0_MSTR_AXI_CLK 93
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#define GCC_PCIE_0_PIPE_CLK 94
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#define GCC_PCIE_0_SLV_AXI_CLK 95
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#define GCC_PCIE_PHY_AUX_CLK 96
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#define GCC_PDM2_CLK 97
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#define GCC_PDM_AHB_CLK 98
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#define GCC_PDM_XO4_CLK 99
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#define GCC_PRNG_AHB_CLK 100
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#define GCC_SDCC2_AHB_CLK 101
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#define GCC_SDCC2_APPS_CLK 102
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#define GCC_SDCC4_AHB_CLK 103
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#define GCC_SDCC4_APPS_CLK 104
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#define GCC_TSIF_AHB_CLK 105
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#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106
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#define GCC_TSIF_REF_CLK 107
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#define GCC_UFS_AHB_CLK 108
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#define GCC_UFS_AXI_CLK 109
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#define GCC_UFS_ICE_CORE_CLK 110
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#define GCC_UFS_PHY_AUX_CLK 111
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#define GCC_UFS_RX_SYMBOL_0_CLK 112
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#define GCC_UFS_RX_SYMBOL_1_CLK 113
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#define GCC_UFS_TX_SYMBOL_0_CLK 114
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#define GCC_UFS_UNIPRO_CORE_CLK 115
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#define GCC_USB30_MASTER_CLK 116
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#define GCC_USB30_MOCK_UTMI_CLK 117
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#define GCC_USB30_SLEEP_CLK 118
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#define GCC_USB3_PHY_AUX_CLK 119
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#define GCC_USB3_PHY_PIPE_CLK 120
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121
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#define GP1_CLK_SRC 122
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#define GP2_CLK_SRC 123
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#define GP3_CLK_SRC 124
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#define GPLL0 125
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#define GPLL0_OUT_EVEN 126
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#define GPLL0_OUT_MAIN 127
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#define GPLL0_OUT_ODD 128
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#define GPLL0_OUT_TEST 129
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#define GPLL1 130
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#define GPLL1_OUT_EVEN 131
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#define GPLL1_OUT_MAIN 132
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#define GPLL1_OUT_ODD 133
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#define GPLL1_OUT_TEST 134
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#define GPLL2 135
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#define GPLL2_OUT_EVEN 136
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#define GPLL2_OUT_MAIN 137
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#define GPLL2_OUT_ODD 138
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#define GPLL2_OUT_TEST 139
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#define GPLL3 140
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#define GPLL3_OUT_EVEN 141
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#define GPLL3_OUT_MAIN 142
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#define GPLL3_OUT_ODD 143
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#define GPLL3_OUT_TEST 144
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#define GPLL4 145
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#define GPLL4_OUT_EVEN 146
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#define GPLL4_OUT_MAIN 147
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#define GPLL4_OUT_ODD 148
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#define GPLL4_OUT_TEST 149
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#define GPLL6 150
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#define GPLL6_OUT_EVEN 151
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#define GPLL6_OUT_MAIN 152
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#define GPLL6_OUT_ODD 153
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#define GPLL6_OUT_TEST 154
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#define HMSS_AHB_CLK_SRC 155
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#define HMSS_RBCPR_CLK_SRC 156
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#define PCIE_AUX_CLK_SRC 157
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#define PDM2_CLK_SRC 158
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#define SDCC2_APPS_CLK_SRC 159
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#define SDCC4_APPS_CLK_SRC 160
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#define TSIF_REF_CLK_SRC 161
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#define UFS_AXI_CLK_SRC 162
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#define USB30_MASTER_CLK_SRC 163
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#define USB30_MOCK_UTMI_CLK_SRC 164
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#define USB3_PHY_AUX_CLK_SRC 165
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#define GCC_USB3_CLKREF_CLK 166
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#define GCC_HDMI_CLKREF_CLK 167
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#define GCC_UFS_CLKREF_CLK 168
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#define GCC_PCIE_CLKREF_CLK 169
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#define GCC_RX1_USB2_CLKREF_CLK 170
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#define PCIE_0_GDSC 0
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#define UFS_GDSC 1
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#define USB_30_GDSC 2
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#define GCC_BLSP1_QUP1_BCR 0
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#define GCC_BLSP1_QUP2_BCR 1
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#define GCC_BLSP1_QUP3_BCR 2
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#define GCC_BLSP1_QUP4_BCR 3
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#define GCC_BLSP1_QUP5_BCR 4
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#define GCC_BLSP1_QUP6_BCR 5
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#define GCC_BLSP2_QUP1_BCR 6
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#define GCC_BLSP2_QUP2_BCR 7
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#define GCC_BLSP2_QUP3_BCR 8
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#define GCC_BLSP2_QUP4_BCR 9
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#define GCC_BLSP2_QUP5_BCR 10
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#define GCC_BLSP2_QUP6_BCR 11
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#define GCC_PCIE_0_BCR 12
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#define GCC_PDM_BCR 13
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#define GCC_SDCC2_BCR 14
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#define GCC_SDCC4_BCR 15
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#define GCC_TSIF_BCR 16
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#define GCC_UFS_BCR 17
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#define GCC_USB_30_BCR 18
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#define GCC_SYSTEM_NOC_BCR 19
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#define GCC_CONFIG_NOC_BCR 20
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#define GCC_AHB2PHY_EAST_BCR 21
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#define GCC_IMEM_BCR 22
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#define GCC_PIMEM_BCR 23
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#define GCC_MMSS_BCR 24
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#define GCC_QDSS_BCR 25
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#define GCC_WCSS_BCR 26
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#define GCC_BLSP1_BCR 27
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#define GCC_BLSP1_UART1_BCR 28
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#define GCC_BLSP1_UART2_BCR 29
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#define GCC_BLSP1_UART3_BCR 30
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#define GCC_CM_PHY_REFGEN1_BCR 31
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#define GCC_CM_PHY_REFGEN2_BCR 32
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#define GCC_BLSP2_BCR 33
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#define GCC_BLSP2_UART1_BCR 34
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#define GCC_BLSP2_UART2_BCR 35
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#define GCC_BLSP2_UART3_BCR 36
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#define GCC_SRAM_SENSOR_BCR 37
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#define GCC_PRNG_BCR 38
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#define GCC_TSIF_0_RESET 39
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#define GCC_TSIF_1_RESET 40
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#define GCC_TCSR_BCR 41
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#define GCC_BOOT_ROM_BCR 42
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#define GCC_MSG_RAM_BCR 43
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#define GCC_TLMM_BCR 44
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#define GCC_MPM_BCR 45
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#define GCC_SEC_CTRL_BCR 46
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#define GCC_SPMI_BCR 47
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#define GCC_SPDM_BCR 48
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#define GCC_CE1_BCR 49
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#define GCC_BIMC_BCR 50
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 51
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#define GCC_SNOC_BUS_TIMEOUT1_BCR 52
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 53
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#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54
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#define GCC_PNOC_BUS_TIMEOUT0_BCR 55
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#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56
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#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57
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#define GCC_CNOC_BUS_TIMEOUT0_BCR 58
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#define GCC_CNOC_BUS_TIMEOUT1_BCR 59
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#define GCC_CNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_CNOC_BUS_TIMEOUT3_BCR 61
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#define GCC_CNOC_BUS_TIMEOUT4_BCR 62
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#define GCC_CNOC_BUS_TIMEOUT5_BCR 63
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#define GCC_CNOC_BUS_TIMEOUT6_BCR 64
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#define GCC_CNOC_BUS_TIMEOUT7_BCR 65
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#define GCC_APB2JTAG_BCR 66
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#define GCC_RBCPR_CX_BCR 67
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#define GCC_RBCPR_MX_BCR 68
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#define GCC_USB3_PHY_BCR 69
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#define GCC_USB3PHY_PHY_BCR 70
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#define GCC_USB3_DP_PHY_BCR 71
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#define GCC_SSC_BCR 72
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#define GCC_SSC_RESET 73
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74
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#define GCC_PCIE_0_LINK_DOWN_BCR 75
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#define GCC_PCIE_0_PHY_BCR 76
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77
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#define GCC_PCIE_PHY_BCR 78
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#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79
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#define GCC_PCIE_PHY_CFG_AHB_BCR 80
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#define GCC_PCIE_PHY_COM_BCR 81
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#define GCC_GPU_BCR 82
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#define GCC_SPSS_BCR 83
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#define GCC_OBT_ODT_BCR 84
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#define GCC_VS_BCR 85
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#define GCC_MSS_VS_RESET 86
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#define GCC_GPU_VS_RESET 87
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#define GCC_APC0_VS_RESET 88
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#define GCC_APC1_VS_RESET 89
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#define GCC_CNOC_BUS_TIMEOUT8_BCR 90
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#define GCC_CNOC_BUS_TIMEOUT9_BCR 91
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#define GCC_CNOC_BUS_TIMEOUT10_BCR 92
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#define GCC_CNOC_BUS_TIMEOUT11_BCR 93
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#define GCC_CNOC_BUS_TIMEOUT12_BCR 94
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#define GCC_CNOC_BUS_TIMEOUT13_BCR 95
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#define GCC_CNOC_BUS_TIMEOUT14_BCR 96
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#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97
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#define GCC_AGGRE1_NOC_BCR 98
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#define GCC_AGGRE2_NOC_BCR 99
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#define GCC_DCC_BCR 100
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#define GCC_QREFS_VBG_CAL_BCR 101
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#define GCC_IPA_BCR 102
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#define GCC_GLM_BCR 103
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#define GCC_SKL_BCR 104
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#define GCC_MSMPU_BCR 105
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#define GCC_QUSB2PHY_PRIM_BCR 106
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#define GCC_QUSB2PHY_SEC_BCR 107
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#endif
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