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c59c015b6a
The emulated (CONFIG_MATH_EMULATION_FULL) PowerPC Floating Point instruction mtfsf does not correctly copy bits from its source register to the Floating Point Status and Register (FPSCR). The error is in the preparation of the mask used to select the bits to be copied from the source to the FPSCR. Execution of the mtfsf instruction does not produce the same results on a MPC8548 platform (emulated floating point) as on MPC7410 or 440EP platforms (hardware floating point). This error has been detected using a Freescale MPC8548 based platform and the patch below tested using that platform. The patch is based on the patch(es) provided by Gabriel Paubert and analysis by Gabriel, James Yang and David Laight. Signed-off-by: Stephen Chivers <schivers@csc.com> Signed-off-by: Gabriel Paubert <paubert@iram.es> Tested-by: Stephen Chivers <schivers@csc.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
#include <linux/types.h>
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#include <linux/errno.h>
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#include <asm/uaccess.h>
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#include <asm/sfp-machine.h>
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#include <math-emu/soft-fp.h>
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int
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mtfsf(unsigned int FM, u32 *frB)
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{
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u32 mask;
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u32 fpscr;
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if (likely(FM == 1))
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mask = 0x0f;
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else if (likely(FM == 0xff))
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mask = ~0;
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else {
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mask = ((FM & 1) |
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((FM << 3) & 0x10) |
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((FM << 6) & 0x100) |
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((FM << 9) & 0x1000) |
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((FM << 12) & 0x10000) |
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((FM << 15) & 0x100000) |
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((FM << 18) & 0x1000000) |
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((FM << 21) & 0x10000000)) * 15;
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}
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fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) &
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~(FPSCR_VX | FPSCR_FEX | 0x800);
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if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
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FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
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FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
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fpscr |= FPSCR_VX;
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/* The bit order of exception enables and exception status
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* is the same. Simply shift and mask to check for enabled
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* exceptions.
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*/
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if (fpscr & (fpscr >> 22) & 0xf8)
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fpscr |= FPSCR_FEX;
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__FPU_FPSCR = fpscr;
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#ifdef DEBUG
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printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR);
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#endif
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return 0;
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}
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