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51dfc6142a
Change SDR50 mode clock source from DLL output clock to PLL open clock 1.HS200 and SDR104 mode select DLL output clock 2.SDR50 mode select PLL open clock Signed-off-by: Fred <fred.ai@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230223120450.16858-1-fredaibayhubtech@126.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
928 lines
25 KiB
C
928 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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* Ernest Zhang <ernest.zhang@bayhubtech.com>
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*/
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#include <linux/pci.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/bitfield.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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/*
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* O2Micro device registers
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*/
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#define O2_SD_MISC_REG5 0x64
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#define O2_SD_LD0_CTRL 0x68
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#define O2_SD_DEV_CTRL 0x88
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_TEST_REG 0xD4
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#define O2_SD_FUNC_REG0 0xDC
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_CLKREQ 0xEC
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#define O2_SD_CAPS 0xE0
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#define O2_SD_ADMA1 0xE2
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#define O2_SD_ADMA2 0xE7
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#define O2_SD_MISC_CTRL2 0xF0
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#define O2_SD_INF_MOD 0xF1
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#define O2_SD_MISC_CTRL4 0xFC
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#define O2_SD_MISC_CTRL 0x1C0
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#define O2_SD_PWR_FORCE_L0 0x0002
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#define O2_SD_TUNING_CTRL 0x300
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#define O2_SD_PLL_SETTING 0x304
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#define O2_SD_MISC_SETTING 0x308
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#define O2_SD_CLK_SETTING 0x328
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#define O2_SD_CAP_REG2 0x330
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#define O2_SD_CAP_REG0 0x334
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#define O2_SD_UHS1_CAP_SETTING 0x33C
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#define O2_SD_DELAY_CTRL 0x350
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#define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354
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#define O2_SD_UHS2_L1_CTRL 0x35C
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#define O2_SD_FUNC_REG3 0x3E0
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#define O2_SD_FUNC_REG4 0x3E4
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#define O2_SD_LED_ENABLE BIT(6)
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#define O2_SD_FREG0_LEDOFF BIT(13)
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#define O2_SD_SEL_DLL BIT(16)
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#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
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#define O2_SD_PHASE_MASK GENMASK(23, 20)
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#define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9)
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#define O2_SD_VENDOR_SETTING 0x110
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#define O2_SD_VENDOR_SETTING2 0x1C8
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#define O2_SD_HW_TUNING_DISABLE BIT(4)
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#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
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#define O2_PLL_FORCE_ACTIVE BIT(18)
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#define O2_PLL_LOCK_STATUS BIT(14)
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#define O2_PLL_SOFT_RESET BIT(12)
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#define O2_DLL_LOCK_STATUS BIT(11)
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#define O2_SD_DETECT_SETTING 0x324
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static const u32 dmdn_table[] = {0x2B1C0000,
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0x2C1A0000, 0x371B0000, 0x35100000};
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#define DMDN_SZ ARRAY_SIZE(dmdn_table)
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struct o2_host {
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u8 dll_adjust_count;
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};
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static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
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{
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ktime_t timeout;
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u32 scratch32;
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/* Wait max 50 ms */
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timeout = ktime_add_ms(ktime_get(), 50);
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
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if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
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== (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
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break;
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if (timedout) {
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pr_err("%s: Card Detect debounce never finished.\n",
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mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return;
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}
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udelay(10);
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}
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}
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static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
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{
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ktime_t timeout;
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u16 scratch;
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u32 scratch32;
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/* PLL software reset */
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scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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scratch32 |= O2_PLL_SOFT_RESET;
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sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
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udelay(1);
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scratch32 &= ~(O2_PLL_SOFT_RESET);
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sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
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/* PLL force active */
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scratch32 |= O2_PLL_FORCE_ACTIVE;
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sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
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/* Wait max 20 ms */
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timeout = ktime_add_ms(ktime_get(), 20);
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while (1) {
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bool timedout = ktime_after(ktime_get(), timeout);
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scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
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if (scratch & O2_PLL_LOCK_STATUS)
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break;
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if (timedout) {
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pr_err("%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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goto out;
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}
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udelay(10);
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}
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/* Wait for card detect finish */
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udelay(1);
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sdhci_o2_wait_card_detect_stable(host);
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out:
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/* Cancel PLL force active */
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scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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scratch32 &= ~O2_PLL_FORCE_ACTIVE;
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sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
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}
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static int sdhci_o2_get_cd(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
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sdhci_o2_enable_internal_clock(host);
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else
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sdhci_o2_wait_card_detect_stable(host);
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return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
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}
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static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
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{
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u32 scratch_32;
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pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= value;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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}
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static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
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{
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return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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}
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/*
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* This function is used to detect dll lock status.
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* Since the dll lock status bit will toggle randomly
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* with very short interval which needs to be polled
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* as fast as possible. Set sleep_us as 1 microsecond.
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*/
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static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
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{
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u32 scratch32 = 0;
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return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
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scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
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}
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static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
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{
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u16 reg;
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/* enable hardware tuning */
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reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
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reg &= ~O2_SD_HW_TUNING_DISABLE;
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sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
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}
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static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int i;
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sdhci_send_tuning(host, opcode);
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for (i = 0; i < 150; i++) {
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u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
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if (ctrl & SDHCI_CTRL_TUNED_CLK) {
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host->tuning_done = true;
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return;
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}
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pr_warn("%s: HW tuning failed !\n",
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mmc_hostname(host->mmc));
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break;
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}
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mdelay(1);
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}
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pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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sdhci_reset_tuning(host);
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}
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/*
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* This function is used to fix o2 dll shift issue.
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* It isn't necessary to detect card present before recovery.
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* Firstly, it is used by bht emmc card, which is embedded.
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* Second, before call recovery card present will be detected
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* outside of the execute tuning function.
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*/
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static int sdhci_o2_dll_recovery(struct sdhci_host *host)
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{
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int ret = 0;
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u8 scratch_8 = 0;
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u32 scratch_32 = 0;
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct sdhci_pci_chip *chip = slot->chip;
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struct o2_host *o2_host = sdhci_pci_priv(slot);
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/* UnLock WP */
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pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch_8);
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scratch_8 &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
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/* Disable clock */
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sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
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/* PLL software reset */
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scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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scratch_32 |= O2_PLL_SOFT_RESET;
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sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
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pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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/* Enable Base Clk setting change */
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scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
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pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
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o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
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/* Enable internal clock */
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scratch_8 = SDHCI_CLOCK_INT_EN;
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sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
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if (sdhci_o2_get_cd(host->mmc)) {
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/*
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* need wait at least 5ms for dll status stable,
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* after enable internal clock
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*/
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usleep_range(5000, 6000);
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if (sdhci_o2_wait_dll_detect_lock(host)) {
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scratch_8 |= SDHCI_CLOCK_CARD_EN;
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sdhci_writeb(host, scratch_8,
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SDHCI_CLOCK_CONTROL);
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ret = 1;
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} else {
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pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
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mmc_hostname(host->mmc),
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o2_host->dll_adjust_count);
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}
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} else {
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pr_err("%s: card present detect failed.\n",
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mmc_hostname(host->mmc));
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break;
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}
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o2_host->dll_adjust_count++;
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}
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if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
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pr_err("%s: DLL adjust over max times\n",
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mmc_hostname(host->mmc));
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/* Lock WP */
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pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch_8);
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scratch_8 |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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return ret;
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}
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static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct sdhci_pci_chip *chip = slot->chip;
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int current_bus_width = 0;
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u32 scratch32 = 0;
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u16 scratch = 0;
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u8 scratch_8 = 0;
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u32 reg_val;
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/*
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* This handler implements the hardware tuning that is specific to
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* this controller. Fall back to the standard method for other TIMING.
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*/
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if ((host->timing != MMC_TIMING_MMC_HS200) &&
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(host->timing != MMC_TIMING_UHS_SDR104) &&
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(host->timing != MMC_TIMING_UHS_SDR50))
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return sdhci_execute_tuning(mmc, opcode);
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if (WARN_ON(!mmc_op_tuning(opcode)))
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return -EINVAL;
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/* Force power mode enter L0 */
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scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
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scratch |= O2_SD_PWR_FORCE_L0;
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sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
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/* Stop clk */
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reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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reg_val &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
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if ((host->timing == MMC_TIMING_MMC_HS200) ||
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(host->timing == MMC_TIMING_UHS_SDR104)) {
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/* UnLock WP */
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pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
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scratch_8 &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
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pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val);
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reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
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reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
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pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
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/* Lock WP */
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pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
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scratch_8 |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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}
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/* Start clk */
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reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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reg_val |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
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/* wait DLL lock, timeout value 5ms */
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if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
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scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
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pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
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mmc_hostname(host->mmc));
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/*
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* Judge the tuning reason, whether caused by dll shift
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* If cause by dll shift, should call sdhci_o2_dll_recovery
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*/
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if (!sdhci_o2_wait_dll_detect_lock(host))
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if (!sdhci_o2_dll_recovery(host)) {
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pr_err("%s: o2 dll recovery failed\n",
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mmc_hostname(host->mmc));
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return -EINVAL;
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}
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/*
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* o2 sdhci host didn't support 8bit emmc tuning
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*/
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if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
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current_bus_width = mmc->ios.bus_width;
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mmc->ios.bus_width = MMC_BUS_WIDTH_4;
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sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
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}
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sdhci_o2_set_tuning_mode(host);
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sdhci_start_tuning(host);
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__sdhci_o2_execute_tuning(host, opcode);
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sdhci_end_tuning(host);
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if (current_bus_width == MMC_BUS_WIDTH_8) {
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mmc->ios.bus_width = MMC_BUS_WIDTH_8;
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sdhci_set_bus_width(host, current_bus_width);
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}
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/* Cancel force power mode enter L0 */
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scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
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scratch &= ~(O2_SD_PWR_FORCE_L0);
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sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
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sdhci_reset(host, SDHCI_RESET_CMD);
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sdhci_reset(host, SDHCI_RESET_DATA);
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host->flags &= ~SDHCI_HS400_TUNING;
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return 0;
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}
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static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
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{
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int ret;
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u32 scratch_32;
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/* Set led of SD host function enable */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~O2_SD_FREG0_LEDOFF;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= O2_SD_LED_ENABLE;
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pci_write_config_dword(chip->pdev,
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O2_SD_TEST_REG, scratch_32);
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}
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static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
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{
|
|
u32 scratch_32;
|
|
int ret;
|
|
/* Improve write performance for SD3.0 */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
|
|
pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
|
|
|
|
/* Enable Link abnormal reset generating Reset */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~((1 << 19) | (1 << 11));
|
|
scratch_32 |= (1 << 10);
|
|
pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
|
|
|
|
/* set card power over current protection */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 |= (1 << 4);
|
|
pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
|
|
|
|
/* adjust the output delay for SD mode */
|
|
pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
|
|
|
|
/* Set the output voltage setting of Aux 1.2v LDO */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(3 << 12);
|
|
pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
|
|
|
|
/* Set Max power supply capability of SD host */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(0x01FE);
|
|
scratch_32 |= 0x00CC;
|
|
pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
|
|
/* Set DLL Tuning Window */
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_TUNING_CTRL, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(0x000000FF);
|
|
scratch_32 |= 0x00000066;
|
|
pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
|
|
|
|
/* Set UHS2 T_EIDLE */
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_UHS2_L1_CTRL, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(0x000000FC);
|
|
scratch_32 |= 0x00000084;
|
|
pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
|
|
|
|
/* Set UHS2 Termination */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~((1 << 21) | (1 << 30));
|
|
|
|
pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
|
|
|
|
/* Set L1 Entrance Timer */
|
|
ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(0xf0000000);
|
|
scratch_32 |= 0x30000000;
|
|
pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_MISC_CTRL4, &scratch_32);
|
|
if (ret)
|
|
return;
|
|
scratch_32 &= ~(0x000f0000);
|
|
scratch_32 |= 0x00080000;
|
|
pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
|
|
}
|
|
|
|
static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
|
|
struct sdhci_host *host)
|
|
{
|
|
int ret;
|
|
|
|
ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
|
|
if (!ret) {
|
|
pr_info("%s: unsupported MSI, use INTx irq\n",
|
|
mmc_hostname(host->mmc));
|
|
return;
|
|
}
|
|
|
|
ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
|
|
PCI_IRQ_MSI | PCI_IRQ_MSIX);
|
|
if (ret < 0) {
|
|
pr_err("%s: enable PCI MSI failed, err=%d\n",
|
|
mmc_hostname(host->mmc), ret);
|
|
return;
|
|
}
|
|
|
|
host->irq = pci_irq_vector(chip->pdev, 0);
|
|
}
|
|
|
|
static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
|
|
{
|
|
/* Enable internal clock */
|
|
clk |= SDHCI_CLOCK_INT_EN;
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
sdhci_o2_enable_internal_clock(host);
|
|
if (sdhci_o2_get_cd(host->mmc)) {
|
|
clk |= SDHCI_CLOCK_CARD_EN;
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
}
|
|
}
|
|
|
|
static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
{
|
|
u16 clk;
|
|
u8 scratch;
|
|
u32 scratch_32;
|
|
struct sdhci_pci_slot *slot = sdhci_priv(host);
|
|
struct sdhci_pci_chip *chip = slot->chip;
|
|
|
|
host->mmc->actual_clock = 0;
|
|
|
|
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
|
|
|
if (clock == 0)
|
|
return;
|
|
|
|
/* UnLock WP */
|
|
pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
|
|
scratch &= 0x7f;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
|
|
pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
|
|
|
|
if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
|
|
o2_pci_set_baseclk(chip, 0x2c280000);
|
|
} else {
|
|
pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
|
|
|
|
if ((scratch_32 & 0xFFFF0000) != 0x25100000)
|
|
o2_pci_set_baseclk(chip, 0x25100000);
|
|
}
|
|
|
|
pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
|
|
scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
|
|
pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
|
|
|
|
/* Lock WP */
|
|
pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
|
|
sdhci_o2_enable_clk(host, clk);
|
|
}
|
|
|
|
static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
|
|
{
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_host *host;
|
|
struct o2_host *o2_host = sdhci_pci_priv(slot);
|
|
u32 reg, caps;
|
|
int ret;
|
|
|
|
chip = slot->chip;
|
|
host = slot->host;
|
|
|
|
o2_host->dll_adjust_count = 0;
|
|
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
|
|
|
|
/*
|
|
* mmc_select_bus_width() will test the bus to determine the actual bus
|
|
* width.
|
|
*/
|
|
if (caps & SDHCI_CAN_DO_8BIT)
|
|
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
|
|
|
|
switch (chip->pdev->device) {
|
|
case PCI_DEVICE_ID_O2_SDS0:
|
|
case PCI_DEVICE_ID_O2_SEABIRD0:
|
|
case PCI_DEVICE_ID_O2_SEABIRD1:
|
|
case PCI_DEVICE_ID_O2_SDS1:
|
|
case PCI_DEVICE_ID_O2_FUJIN2:
|
|
reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
|
|
if (reg & 0x1)
|
|
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
|
|
|
|
host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
|
|
|
|
sdhci_pci_o2_enable_msi(chip, host);
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_MISC_SETTING, ®);
|
|
if (ret)
|
|
return -EIO;
|
|
if (reg & (1 << 4)) {
|
|
pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
|
|
mmc_hostname(host->mmc));
|
|
host->flags &= ~SDHCI_SIGNALING_330;
|
|
host->flags |= SDHCI_SIGNALING_180;
|
|
host->mmc->caps2 |= MMC_CAP2_NO_SD;
|
|
host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_DETECT_SETTING, 3);
|
|
}
|
|
|
|
slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
|
|
}
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
|
|
slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
|
|
host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
|
|
host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
|
|
}
|
|
|
|
host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
|
|
|
|
if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
|
|
break;
|
|
/* set dll watch dog timer */
|
|
reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
|
|
reg |= (1 << 12);
|
|
sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
|
|
{
|
|
int ret;
|
|
u8 scratch;
|
|
u32 scratch_32;
|
|
|
|
switch (chip->pdev->device) {
|
|
case PCI_DEVICE_ID_O2_8220:
|
|
case PCI_DEVICE_ID_O2_8221:
|
|
case PCI_DEVICE_ID_O2_8320:
|
|
case PCI_DEVICE_ID_O2_8321:
|
|
/* This extra setup is required due to broken ADMA. */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch &= 0x7f;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
/* Set Multi 3 to VCC3V# */
|
|
pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
|
|
|
|
/* Disable CLK_REQ# support after media DET */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_CLKREQ, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x20;
|
|
pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
|
|
|
|
/* Choose capabilities, enable SDMA. We have to write 0x01
|
|
* to the capabilities register first to unlock it.
|
|
*/
|
|
ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x01;
|
|
pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
|
|
pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
|
|
|
|
/* Disable ADMA1/2 */
|
|
pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
|
|
pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
|
|
|
|
/* Disable the infinite transfer mode */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_INF_MOD, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x08;
|
|
pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
|
|
|
|
/* Lock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
break;
|
|
case PCI_DEVICE_ID_O2_SDS0:
|
|
case PCI_DEVICE_ID_O2_SDS1:
|
|
case PCI_DEVICE_ID_O2_FUJIN2:
|
|
/* UnLock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
|
|
scratch &= 0x7f;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
/* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
|
|
if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG0,
|
|
&scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
|
|
|
|
/* Check Whether subId is 0x11 or 0x12 */
|
|
if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
|
|
scratch_32 = 0x25100000;
|
|
|
|
o2_pci_set_baseclk(chip, scratch_32);
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4,
|
|
&scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable Base Clk setting change */
|
|
scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4,
|
|
scratch_32);
|
|
|
|
/* Set Tuning Window to 4 */
|
|
pci_write_config_byte(chip->pdev,
|
|
O2_SD_TUNING_CTRL, 0x44);
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Enable 8520 led function */
|
|
o2_pci_led_enable(chip);
|
|
|
|
/* Set timeout CLK */
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_CLK_SETTING, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
|
|
scratch_32 &= ~(0xFF00);
|
|
scratch_32 |= 0x07E0C800;
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_CLK_SETTING, scratch_32);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_CLKREQ, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
scratch_32 |= 0x3;
|
|
pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
|
|
scratch_32 &= ~(0x1F3F070E);
|
|
scratch_32 |= 0x18270106;
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
|
|
/* Disable UHS1 funciton */
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_CAP_REG2, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
scratch_32 &= ~(0xE0);
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_CAP_REG2, scratch_32);
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
|
|
sdhci_pci_o2_fujin2_pci_init(chip);
|
|
|
|
/* Lock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
break;
|
|
case PCI_DEVICE_ID_O2_SEABIRD0:
|
|
case PCI_DEVICE_ID_O2_SEABIRD1:
|
|
/* UnLock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
|
|
scratch &= 0x7f;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if ((scratch_32 & 0xff000000) == 0x01000000) {
|
|
scratch_32 &= 0x0000FFFF;
|
|
scratch_32 |= 0x1F340000;
|
|
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
} else {
|
|
scratch_32 &= 0x0000FFFF;
|
|
scratch_32 |= 0x25100000;
|
|
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4,
|
|
&scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
scratch_32 |= (1 << 22);
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4, scratch_32);
|
|
}
|
|
|
|
/* Set Tuning Windows to 5 */
|
|
pci_write_config_byte(chip->pdev,
|
|
O2_SD_TUNING_CTRL, 0x55);
|
|
//Adjust 1st and 2nd CD debounce time
|
|
pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
|
|
scratch_32 &= 0xFFE7FFFF;
|
|
scratch_32 |= 0x00180000;
|
|
pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
|
|
pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
|
|
/* Lock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
|
|
{
|
|
sdhci_pci_o2_probe(chip);
|
|
return sdhci_pci_resume_host(chip);
|
|
}
|
|
#endif
|
|
|
|
static const struct sdhci_ops sdhci_pci_o2_ops = {
|
|
.set_clock = sdhci_pci_o2_set_clock,
|
|
.enable_dma = sdhci_pci_enable_dma,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.reset = sdhci_reset,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
};
|
|
|
|
const struct sdhci_pci_fixes sdhci_o2 = {
|
|
.probe = sdhci_pci_o2_probe,
|
|
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
|
.quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
|
|
.probe_slot = sdhci_pci_o2_probe_slot,
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.resume = sdhci_pci_o2_resume,
|
|
#endif
|
|
.ops = &sdhci_pci_o2_ops,
|
|
.priv_size = sizeof(struct o2_host),
|
|
};
|