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b1f9f4541e
Add support for PHY interface built into ahci controller implemented
in UniPhier Pro4 SoC.
Pro4 SoC distinguishes it from other SoCs as "legacy" SoC, which has GIO
clock line. And Pro4 AHCI-PHY needs to control additional reset lines
("pm", "tx", and "rx").
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-9-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# PHY drivers for Socionext platforms.
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#
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config PHY_UNIPHIER_USB2
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tristate "UniPhier USB2 PHY driver"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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select GENERIC_PHY
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select MFD_SYSCON
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help
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Enable this to support USB PHY implemented on USB2 controller
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on UniPhier SoCs. This driver provides interface to interact
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with USB 2.0 PHY that is part of the UniPhier SoC.
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In case of Pro4, it is necessary to specify this USB2 PHY instead
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of USB3 HS-PHY.
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config PHY_UNIPHIER_USB3
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tristate "UniPhier USB3 PHY driver"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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select GENERIC_PHY
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help
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Enable this to support USB PHY implemented in USB3 controller
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on UniPhier SoCs. This controller supports USB3.0 and lower speed.
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config PHY_UNIPHIER_PCIE
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tristate "Uniphier PHY driver for PCIe controller"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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default PCIE_UNIPHIER
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select GENERIC_PHY
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help
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Enable this to support PHY implemented in PCIe controller
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on UniPhier SoCs. This driver supports LD20 and PXs3 SoCs.
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config PHY_UNIPHIER_AHCI
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tristate "UniPhier AHCI PHY driver"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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default SATA_AHCI_PLATFORM
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select GENERIC_PHY
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help
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Enable this to support PHY implemented in AHCI controller
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on UniPhier SoCs. This driver supports Pro4, PXs2 and PXs3 SoCs.
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