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8391c6cb24
Add entry for RTC and Power Controller to MT6323. Signed-off-by: Josef Friedl <josef.friedl@speed.at> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Lee Jones <lee.jones@linaro.org>
235 lines
5.7 KiB
C
235 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/mt6323/core.h>
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#include <linux/mfd/mt6397/core.h>
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#include <linux/mfd/mt6323/registers.h>
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#include <linux/mfd/mt6397/registers.h>
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#define MT6323_RTC_BASE 0x8000
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#define MT6323_RTC_SIZE 0x40
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#define MT6397_RTC_BASE 0xe000
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#define MT6397_RTC_SIZE 0x3e
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#define MT6323_PWRC_BASE 0x8000
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#define MT6323_PWRC_SIZE 0x40
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static const struct resource mt6323_rtc_resources[] = {
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DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
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};
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static const struct resource mt6397_rtc_resources[] = {
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DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
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DEFINE_RES_IRQ(MT6397_IRQ_RTC),
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};
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static const struct resource mt6323_keys_resources[] = {
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
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DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
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};
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static const struct resource mt6397_keys_resources[] = {
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DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
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DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
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};
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static const struct resource mt6323_pwrc_resources[] = {
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DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
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};
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static const struct mfd_cell mt6323_devs[] = {
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{
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.name = "mt6323-rtc",
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.num_resources = ARRAY_SIZE(mt6323_rtc_resources),
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.resources = mt6323_rtc_resources,
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.of_compatible = "mediatek,mt6323-rtc",
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}, {
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.name = "mt6323-regulator",
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.of_compatible = "mediatek,mt6323-regulator"
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}, {
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.name = "mt6323-led",
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.of_compatible = "mediatek,mt6323-led"
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6323_keys_resources),
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.resources = mt6323_keys_resources,
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.of_compatible = "mediatek,mt6323-keys"
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}, {
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.name = "mt6323-pwrc",
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.num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
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.resources = mt6323_pwrc_resources,
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.of_compatible = "mediatek,mt6323-pwrc"
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},
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};
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static const struct mfd_cell mt6397_devs[] = {
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{
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.name = "mt6397-rtc",
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.num_resources = ARRAY_SIZE(mt6397_rtc_resources),
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.resources = mt6397_rtc_resources,
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.of_compatible = "mediatek,mt6397-rtc",
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}, {
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.name = "mt6397-regulator",
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.of_compatible = "mediatek,mt6397-regulator",
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}, {
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.name = "mt6397-codec",
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.of_compatible = "mediatek,mt6397-codec",
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}, {
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.name = "mt6397-clk",
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.of_compatible = "mediatek,mt6397-clk",
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}, {
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.name = "mt6397-pinctrl",
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.of_compatible = "mediatek,mt6397-pinctrl",
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}, {
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.name = "mtk-pmic-keys",
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.num_resources = ARRAY_SIZE(mt6397_keys_resources),
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.resources = mt6397_keys_resources,
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.of_compatible = "mediatek,mt6397-keys"
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}
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};
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#ifdef CONFIG_PM_SLEEP
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static int mt6397_irq_suspend(struct device *dev)
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{
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struct mt6397_chip *chip = dev_get_drvdata(dev);
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regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
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regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
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enable_irq_wake(chip->irq);
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return 0;
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}
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static int mt6397_irq_resume(struct device *dev)
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{
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struct mt6397_chip *chip = dev_get_drvdata(dev);
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regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
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regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
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disable_irq_wake(chip->irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
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mt6397_irq_resume);
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static int mt6397_probe(struct platform_device *pdev)
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{
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int ret;
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unsigned int id;
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struct mt6397_chip *pmic;
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pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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pmic->dev = &pdev->dev;
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/*
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* mt6397 MFD is child device of soc pmic wrapper.
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* Regmap is set from its parent.
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*/
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pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!pmic->regmap)
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return -ENODEV;
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platform_set_drvdata(pdev, pmic);
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ret = regmap_read(pmic->regmap, MT6397_CID, &id);
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if (ret) {
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dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
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return ret;
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}
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pmic->irq = platform_get_irq(pdev, 0);
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if (pmic->irq <= 0)
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return pmic->irq;
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switch (id & 0xff) {
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case MT6323_CHIP_ID:
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pmic->int_con[0] = MT6323_INT_CON0;
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pmic->int_con[1] = MT6323_INT_CON1;
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pmic->int_status[0] = MT6323_INT_STATUS0;
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pmic->int_status[1] = MT6323_INT_STATUS1;
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ret = mt6397_irq_init(pmic);
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if (ret)
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return ret;
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ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
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ARRAY_SIZE(mt6323_devs), NULL,
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0, pmic->irq_domain);
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break;
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case MT6391_CHIP_ID:
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case MT6397_CHIP_ID:
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pmic->int_con[0] = MT6397_INT_CON0;
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pmic->int_con[1] = MT6397_INT_CON1;
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pmic->int_status[0] = MT6397_INT_STATUS0;
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pmic->int_status[1] = MT6397_INT_STATUS1;
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ret = mt6397_irq_init(pmic);
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if (ret)
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return ret;
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ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
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ARRAY_SIZE(mt6397_devs), NULL,
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0, pmic->irq_domain);
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break;
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default:
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dev_err(&pdev->dev, "unsupported chip: %d\n", id);
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return -ENODEV;
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}
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if (ret) {
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irq_domain_remove(pmic->irq_domain);
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dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
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}
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return ret;
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}
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static const struct of_device_id mt6397_of_match[] = {
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{ .compatible = "mediatek,mt6397" },
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{ .compatible = "mediatek,mt6323" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mt6397_of_match);
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static const struct platform_device_id mt6397_id[] = {
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{ "mt6397", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(platform, mt6397_id);
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static struct platform_driver mt6397_driver = {
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.probe = mt6397_probe,
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.driver = {
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.name = "mt6397",
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.of_match_table = of_match_ptr(mt6397_of_match),
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.pm = &mt6397_pm_ops,
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},
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.id_table = mt6397_id,
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};
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module_platform_driver(mt6397_driver);
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MODULE_AUTHOR("Flora Fu, MediaTek");
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MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
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MODULE_LICENSE("GPL");
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