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0f77ce26eb
This reverts commit 7b8e0188fa.
Initially, STiH410-B2260 was supposed to be secured, that's why
l2c_write_sec was stubbed to avoid secure register access from
non secure world.
But by default, STiH410-B2260 is running in non secure mode,
so L2 cache register accesses are authorized, l2c_write_sec stub
is not needed.
With this patch, L2 cache is configured and performance are enhanced.
Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Alain Volmat <alain.volmat@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
32 lines
763 B
C
32 lines
763 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*/
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#include <linux/irq.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include "smp.h"
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static const char *const stih41x_dt_match[] __initconst = {
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"st,stih415",
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"st,stih416",
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"st,stih407",
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"st,stih410",
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"st,stih418",
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NULL
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};
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DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
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.dt_compat = stih41x_dt_match,
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.l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE |
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L310_AUX_CTRL_DATA_PREFETCH |
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L310_AUX_CTRL_INSTR_PREFETCH |
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L2C_AUX_CTRL_WAY_SIZE(4),
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.l2c_aux_mask = 0xc0000fff,
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.smp = smp_ops(sti_smp_ops),
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MACHINE_END
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