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Broadcom has released cards based on a new AMBA-based bus type. From a programming point of view, this new bus type differs from AMBA and does not use AMBA common registers. It also differs enough from SSB. We decided that a new bus driver is needed to keep the code clean. In its current form, the driver detects devices present on the bus and registers them in the system. It allows registering BCMA drivers for specified bus devices and provides them basic operations. The bus driver itself includes two important bus managing drivers: ChipCommon core driver and PCI(c) core driver. They are early used to allow correct initialization. Currently code is limited to supporting buses on PCI(e) devices, however the driver is designed to be used also on other hosts. The host abstraction layer is implemented and already used for PCI(e). Support for PCI(e) hosts is working and seems to be stable (access to 80211 core was tested successfully on a few devices). We can still optimize it by using some fixed windows, but this can be done later without affecting any external code. Windows are just ranges in MMIO used for accessing cores on the bus. Cc: Greg KH <greg@kroah.com> Cc: Michael Büsch <mb@bu3sch.de> Cc: Larry Finger <Larry.Finger@lwfinger.net> Cc: George Kashperko <george@znau.edu.ua> Cc: Arend van Spriel <arend@broadcom.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <rmk@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andy Botting <andy@andybotting.com> Cc: linuxdriverproject <devel@linuxdriverproject.org> Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* Broadcom specific AMBA
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* ChipCommon core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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u32 mask, u32 value)
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{
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value &= mask;
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value |= bcma_cc_read32(cc, offset) & ~mask;
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bcma_cc_write32(cc, offset, value);
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return value;
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}
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void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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{
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if (cc->core->id.rev >= 11)
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cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
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if (cc->core->id.rev >= 35)
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cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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bcma_cc_write32(cc, 0x58, 0);
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bcma_cc_write32(cc, 0x5C, 0);
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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bcma_pmu_init(cc);
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if (cc->capabilities & BCMA_CC_CAP_PCTL)
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pr_err("Power control not implemented!\n");
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
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{
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/* instant NMI */
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bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
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}
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
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}
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
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}
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u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
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{
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return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
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}
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u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
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}
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
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}
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u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
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u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
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}
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u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
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{
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return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
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}
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