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540 lines
13 KiB
Plaintext
540 lines
13 KiB
Plaintext
/* fuc microcode for nvc0 PGRAPH/GPC
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*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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/* To build:
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* m4 nvc0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grgpc.fuc.h
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*/
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/* TODO
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* - bracket certain functions with scratch writes, useful for debugging
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* - watchdog timer around ctx operations
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*/
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.section #nvc0_grgpc_data
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include(`nvc0_graph.fuc')
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gpc_id: .b32 0
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gpc_mmio_list_head: .b32 0
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gpc_mmio_list_tail: .b32 0
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tpc_count: .b32 0
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tpc_mask: .b32 0
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tpc_mmio_list_head: .b32 0
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tpc_mmio_list_tail: .b32 0
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cmd_queue: queue_init
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// chipset descriptions
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chipsets:
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.b8 0xc0 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc0_tpc_mmio_tail
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.b8 0xc1 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc1_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc1_tpc_mmio_tail
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.b8 0xc3 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc3_tpc_mmio_tail
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.b8 0xc4 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc3_tpc_mmio_tail
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.b8 0xc8 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc0_tpc_mmio_tail
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.b8 0xce 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvc3_tpc_mmio_tail
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.b8 0xcf 0 0 0
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.b16 #nvc0_gpc_mmio_head
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.b16 #nvc0_gpc_mmio_tail
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.b16 #nvc0_tpc_mmio_head
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.b16 #nvcf_tpc_mmio_tail
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.b8 0xd9 0 0 0
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.b16 #nvd9_gpc_mmio_head
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.b16 #nvd9_gpc_mmio_tail
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.b16 #nvd9_tpc_mmio_head
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.b16 #nvd9_tpc_mmio_tail
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.b8 0 0 0 0
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// GPC mmio lists
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nvc0_gpc_mmio_head:
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mmctx_data(0x000380, 1)
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mmctx_data(0x000400, 6)
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mmctx_data(0x000450, 9)
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mmctx_data(0x000600, 1)
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mmctx_data(0x000684, 1)
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mmctx_data(0x000700, 5)
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mmctx_data(0x000800, 1)
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mmctx_data(0x000808, 3)
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mmctx_data(0x000828, 1)
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mmctx_data(0x000830, 1)
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mmctx_data(0x0008d8, 1)
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mmctx_data(0x0008e0, 1)
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mmctx_data(0x0008e8, 6)
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mmctx_data(0x00091c, 1)
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mmctx_data(0x000924, 3)
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mmctx_data(0x000b00, 1)
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mmctx_data(0x000b08, 6)
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mmctx_data(0x000bb8, 1)
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mmctx_data(0x000c08, 1)
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mmctx_data(0x000c10, 8)
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mmctx_data(0x000c80, 1)
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mmctx_data(0x000c8c, 1)
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mmctx_data(0x001000, 3)
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mmctx_data(0x001014, 1)
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nvc0_gpc_mmio_tail:
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mmctx_data(0x000c6c, 1);
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nvc1_gpc_mmio_tail:
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nvd9_gpc_mmio_head:
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mmctx_data(0x000380, 1)
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mmctx_data(0x000400, 2)
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mmctx_data(0x00040c, 3)
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mmctx_data(0x000450, 9)
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mmctx_data(0x000600, 1)
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mmctx_data(0x000684, 1)
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mmctx_data(0x000700, 5)
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mmctx_data(0x000800, 1)
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mmctx_data(0x000808, 3)
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mmctx_data(0x000828, 1)
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mmctx_data(0x000830, 1)
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mmctx_data(0x0008d8, 1)
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mmctx_data(0x0008e0, 1)
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mmctx_data(0x0008e8, 6)
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mmctx_data(0x00091c, 1)
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mmctx_data(0x000924, 3)
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mmctx_data(0x000b00, 1)
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mmctx_data(0x000b08, 6)
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mmctx_data(0x000bb8, 1)
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mmctx_data(0x000c08, 1)
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mmctx_data(0x000c10, 8)
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mmctx_data(0x000c6c, 1)
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mmctx_data(0x000c80, 1)
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mmctx_data(0x000c8c, 1)
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mmctx_data(0x001000, 3)
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mmctx_data(0x001014, 1)
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nvd9_gpc_mmio_tail:
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// TPC mmio lists
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nvc0_tpc_mmio_head:
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mmctx_data(0x000018, 1)
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mmctx_data(0x00003c, 1)
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mmctx_data(0x000048, 1)
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mmctx_data(0x000064, 1)
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mmctx_data(0x000088, 1)
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mmctx_data(0x000200, 6)
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mmctx_data(0x00021c, 2)
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mmctx_data(0x000300, 6)
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mmctx_data(0x0003d0, 1)
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mmctx_data(0x0003e0, 2)
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mmctx_data(0x000400, 3)
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mmctx_data(0x000420, 1)
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mmctx_data(0x0004b0, 1)
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mmctx_data(0x0004e8, 1)
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mmctx_data(0x0004f4, 1)
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mmctx_data(0x000520, 2)
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mmctx_data(0x000604, 4)
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mmctx_data(0x000644, 20)
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mmctx_data(0x000698, 1)
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mmctx_data(0x000750, 2)
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nvc0_tpc_mmio_tail:
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mmctx_data(0x000758, 1)
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mmctx_data(0x0002c4, 1)
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mmctx_data(0x0006e0, 1)
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nvcf_tpc_mmio_tail:
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mmctx_data(0x0004bc, 1)
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nvc3_tpc_mmio_tail:
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mmctx_data(0x000544, 1)
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nvc1_tpc_mmio_tail:
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nvd9_tpc_mmio_head:
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mmctx_data(0x000018, 1)
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mmctx_data(0x00003c, 1)
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mmctx_data(0x000048, 1)
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mmctx_data(0x000064, 1)
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mmctx_data(0x000088, 1)
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mmctx_data(0x000200, 6)
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mmctx_data(0x00021c, 2)
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mmctx_data(0x0002c4, 1)
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mmctx_data(0x000300, 6)
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mmctx_data(0x0003d0, 1)
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mmctx_data(0x0003e0, 2)
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mmctx_data(0x000400, 3)
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mmctx_data(0x000420, 3)
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mmctx_data(0x0004b0, 1)
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mmctx_data(0x0004e8, 1)
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mmctx_data(0x0004f4, 1)
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mmctx_data(0x000520, 2)
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mmctx_data(0x000544, 1)
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mmctx_data(0x000604, 4)
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mmctx_data(0x000644, 20)
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mmctx_data(0x000698, 1)
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mmctx_data(0x0006e0, 1)
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mmctx_data(0x000750, 3)
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nvd9_tpc_mmio_tail:
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.section #nvc0_grgpc_code
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bra #init
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define(`include_code')
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include(`nvc0_graph.fuc')
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// reports an exception to the host
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//
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// In: $r15 error code (see nvc0_graph.fuc)
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//
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error:
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push $r14
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mov $r14 -0x67ec // 0x9814
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sethi $r14 0x400000
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call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
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add b32 $r14 0x41c
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mov $r15 1
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call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
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pop $r14
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ret
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// GPC fuc initialisation, executed by triggering ucode start, will
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// fall through to main loop after completion.
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//
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// Input:
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// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
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// CC_SCRATCH[1]: context base
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//
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// Output:
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// CC_SCRATCH[0]:
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// 31:31: set to signal completion
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// CC_SCRATCH[1]:
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// 31:0: GPC context size
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//
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init:
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clear b32 $r0
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mov $sp $r0
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// enable fifo access
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mov $r1 0x1200
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mov $r2 2
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iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
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// setup i0 handler, and route all interrupts to it
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mov $r1 #ih
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mov $iv0 $r1
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mov $r1 0x400
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iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
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// enable fifo interrupt
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mov $r2 4
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iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
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// enable interrupts
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bset $flags ie0
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// figure out which GPC we are, and how many TPCs we have
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mov $r1 0x608
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shl b32 $r1 6
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iord $r2 I[$r1 + 0x000] // UNITS
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mov $r3 1
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and $r2 0x1f
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shl b32 $r3 $r2
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sub b32 $r3 1
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st b32 D[$r0 + #tpc_count] $r2
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st b32 D[$r0 + #tpc_mask] $r3
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add b32 $r1 0x400
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iord $r2 I[$r1 + 0x000] // MYINDEX
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st b32 D[$r0 + #gpc_id] $r2
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// find context data for this chipset
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mov $r2 0x800
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shl b32 $r2 6
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iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
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mov $r1 #chipsets - 12
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init_find_chipset:
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add b32 $r1 12
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ld b32 $r3 D[$r1 + 0x00]
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cmpu b32 $r3 $r2
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bra e #init_context
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cmpu b32 $r3 0
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bra ne #init_find_chipset
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// unknown chipset
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ret
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// initialise context base, and size tracking
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init_context:
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mov $r2 0x800
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shl b32 $r2 6
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iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
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clear b32 $r3 // track GPC context size here
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// set mmctx base addresses now so we don't have to do it later,
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// they don't currently ever change
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mov $r4 0x700
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shl b32 $r4 6
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shr b32 $r5 $r2 8
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iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
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iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
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// calculate GPC mmio context size, store the chipset-specific
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// mmio list pointers somewhere we can get at them later without
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// re-parsing the chipset list
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clear b32 $r14
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clear b32 $r15
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ld b16 $r14 D[$r1 + 4]
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ld b16 $r15 D[$r1 + 6]
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st b16 D[$r0 + #gpc_mmio_list_head] $r14
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st b16 D[$r0 + #gpc_mmio_list_tail] $r15
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call #mmctx_size
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add b32 $r2 $r15
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add b32 $r3 $r15
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// calculate per-TPC mmio context size, store the list pointers
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ld b16 $r14 D[$r1 + 8]
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ld b16 $r15 D[$r1 + 10]
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st b16 D[$r0 + #tpc_mmio_list_head] $r14
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st b16 D[$r0 + #tpc_mmio_list_tail] $r15
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call #mmctx_size
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ld b32 $r14 D[$r0 + #tpc_count]
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mulu $r14 $r15
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add b32 $r2 $r14
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add b32 $r3 $r14
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// round up base/size to 256 byte boundary (for strand SWBASE)
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add b32 $r4 0x1300
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shr b32 $r3 2
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iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
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shr b32 $r2 8
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shr b32 $r3 6
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add b32 $r2 1
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add b32 $r3 1
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shl b32 $r2 8
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shl b32 $r3 8
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// calculate size of strand context data
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mov b32 $r15 $r2
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call #strand_ctx_init
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add b32 $r3 $r15
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// save context size, and tell HUB we're done
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mov $r1 0x800
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shl b32 $r1 6
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iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
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add b32 $r1 0x800
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clear b32 $r2
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bset $r2 31
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iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
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// Main program loop, very simple, sleeps until woken up by the interrupt
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// handler, pulls a command from the queue and executes its handler
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//
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main:
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bset $flags $p0
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sleep $p0
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mov $r13 #cmd_queue
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call #queue_get
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bra $p1 #main
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// 0x0000-0x0003 are all context transfers
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cmpu b32 $r14 0x04
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bra nc #main_not_ctx_xfer
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// fetch $flags and mask off $p1/$p2
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mov $r1 $flags
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mov $r2 0x0006
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not b32 $r2
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and $r1 $r2
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// set $p1/$p2 according to transfer type
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shl b32 $r14 1
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or $r1 $r14
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mov $flags $r1
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// transfer context data
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call #ctx_xfer
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bra #main
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main_not_ctx_xfer:
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shl b32 $r15 $r14 16
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or $r15 E_BAD_COMMAND
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call #error
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bra #main
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// interrupt handler
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ih:
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push $r8
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mov $r8 $flags
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push $r8
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push $r9
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push $r10
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push $r11
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push $r13
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push $r14
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push $r15
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// incoming fifo command?
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iord $r10 I[$r0 + 0x200] // INTR
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and $r11 $r10 0x00000004
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bra e #ih_no_fifo
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// queue incoming fifo command for later processing
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mov $r11 0x1900
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mov $r13 #cmd_queue
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iord $r14 I[$r11 + 0x100] // FIFO_CMD
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iord $r15 I[$r11 + 0x000] // FIFO_DATA
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call #queue_put
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add b32 $r11 0x400
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mov $r14 1
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iowr I[$r11 + 0x000] $r14 // FIFO_ACK
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// ack, and wake up main()
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ih_no_fifo:
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iowr I[$r0 + 0x100] $r10 // INTR_ACK
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pop $r15
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pop $r14
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pop $r13
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pop $r11
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pop $r10
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pop $r9
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pop $r8
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mov $flags $r8
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pop $r8
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bclr $flags $p0
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iret
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// Set this GPC's bit in HUB_BAR, used to signal completion of various
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// activities to the HUB fuc
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//
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hub_barrier_done:
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mov $r15 1
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ld b32 $r14 D[$r0 + #gpc_id]
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shl b32 $r15 $r14
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mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
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sethi $r14 0x400000
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call #nv_wr32
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ret
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// Disables various things, waits a bit, and re-enables them..
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//
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// Not sure how exactly this helps, perhaps "ENABLE" is not such a
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// good description for the bits we turn off? Anyways, without this,
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// funny things happen.
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//
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ctx_redswitch:
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mov $r14 0x614
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shl b32 $r14 6
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mov $r15 0x020
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iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
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mov $r15 8
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ctx_redswitch_delay:
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sub b32 $r15 1
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bra ne #ctx_redswitch_delay
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mov $r15 0xa20
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iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
|
|
ret
|
|
|
|
// Transfer GPC context data between GPU and storage area
|
|
//
|
|
// In: $r15 context base address
|
|
// $p1 clear on save, set on load
|
|
// $p2 set if opposite direction done/will be done, so:
|
|
// on save it means: "a load will follow this save"
|
|
// on load it means: "a save preceeded this load"
|
|
//
|
|
ctx_xfer:
|
|
// set context base address
|
|
mov $r1 0xa04
|
|
shl b32 $r1 6
|
|
iowr I[$r1 + 0x000] $r15// MEM_BASE
|
|
bra not $p1 #ctx_xfer_not_load
|
|
call #ctx_redswitch
|
|
ctx_xfer_not_load:
|
|
|
|
// strands
|
|
mov $r1 0x4afc
|
|
sethi $r1 0x20000
|
|
mov $r2 0xc
|
|
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
|
|
call #strand_wait
|
|
mov $r2 0x47fc
|
|
sethi $r2 0x20000
|
|
iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
|
|
xbit $r2 $flags $p1
|
|
add b32 $r2 3
|
|
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
|
|
|
|
// mmio context
|
|
xbit $r10 $flags $p1 // direction
|
|
or $r10 2 // first
|
|
mov $r11 0x0000
|
|
sethi $r11 0x500000
|
|
ld b32 $r12 D[$r0 + #gpc_id]
|
|
shl b32 $r12 15
|
|
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
|
|
ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
|
|
ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
|
|
mov $r14 0 // not multi
|
|
call #mmctx_xfer
|
|
|
|
// per-TPC mmio context
|
|
xbit $r10 $flags $p1 // direction
|
|
or $r10 4 // last
|
|
mov $r11 0x4000
|
|
sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
|
|
ld b32 $r12 D[$r0 + #gpc_id]
|
|
shl b32 $r12 15
|
|
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
|
|
ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
|
|
ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
|
|
ld b32 $r15 D[$r0 + #tpc_mask]
|
|
mov $r14 0x800 // stride = 0x800
|
|
call #mmctx_xfer
|
|
|
|
// wait for strands to finish
|
|
call #strand_wait
|
|
|
|
// if load, or a save without a load following, do some
|
|
// unknown stuff that's done after finishing a block of
|
|
// strand commands
|
|
bra $p1 #ctx_xfer_post
|
|
bra not $p2 #ctx_xfer_done
|
|
ctx_xfer_post:
|
|
mov $r1 0x4afc
|
|
sethi $r1 0x20000
|
|
mov $r2 0xd
|
|
iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
|
|
call #strand_wait
|
|
|
|
// mark completion in HUB's barrier
|
|
ctx_xfer_done:
|
|
call #hub_barrier_done
|
|
ret
|
|
|
|
.align 256
|