linux/arch/riscv/mm
Linus Torvalds 56d428ae1c RISC-V Patches for the 6.7 Merge Window, Part 2
* Support for handling misaligned accesses in S-mode.
 * Probing for misaligned access support is now properly cached and
   handled in parallel.
 * PTDUMP now reflects the SW reserved bits, as well as the PBMT and
   NAPOT extensions.
 * Performance improvements for TLB flushing.
 * Support for many new relocations in the module loader.
 * Various bug fixes and cleanups.
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Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - Support for handling misaligned accesses in S-mode

 - Probing for misaligned access support is now properly cached and
   handled in parallel

 - PTDUMP now reflects the SW reserved bits, as well as the PBMT and
   NAPOT extensions

 - Performance improvements for TLB flushing

 - Support for many new relocations in the module loader

 - Various bug fixes and cleanups

* tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits)
  riscv: Optimize bitops with Zbb extension
  riscv: Rearrange hwcap.h and cpufeature.h
  drivers: perf: Do not broadcast to other cpus when starting a counter
  drivers: perf: Check find_first_bit() return value
  of: property: Add fw_devlink support for msi-parent
  RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
  riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings
  riscv: Don't use PGD entries for the linear mapping
  RISC-V: Probe misaligned access speed in parallel
  RISC-V: Remove __init on unaligned_emulation_finish()
  RISC-V: Show accurate per-hart isa in /proc/cpuinfo
  RISC-V: Don't rely on positional structure initialization
  riscv: Add tests for riscv module loading
  riscv: Add remaining module relocations
  riscv: Avoid unaligned access when relocating modules
  riscv: split cache ops out of dma-noncoherent.c
  riscv: Improve flush_tlb_kernel_range()
  riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
  riscv: Improve flush_tlb_range() for hugetlb pages
  riscv: Improve tlb_flush()
  ...
2023-11-10 09:23:17 -08:00
..
cache-ops.c riscv: split cache ops out of dma-noncoherent.c 2023-11-07 09:37:42 -08:00
cacheflush.c RISC-V: cacheflush: Initialize CBO variables on ACPI systems 2023-10-26 09:40:34 -07:00
context.c riscv: mm: use bitmap_zero() API 2023-08-31 00:18:29 -07:00
dma-noncoherent.c riscv: split cache ops out of dma-noncoherent.c 2023-11-07 09:37:42 -08:00
extable.c riscv: extable: fix err reg writing in dedicated uaccess handler 2022-02-08 17:02:47 -08:00
fault.c riscv: handle VM_FAULT_[HWPOISON|HWPOISON_LARGE] faults instead of panicking 2023-10-06 14:11:38 -07:00
hugetlbpage.c riscv: fix set_huge_pte_at() for NAPOT mappings when a swap entry is set 2023-10-06 14:11:38 -07:00
init.c RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00
kasan_init.c RISC-V Patches for the 6.6 Merge Window, Part 1 2023-09-01 08:09:48 -07:00
Makefile riscv: split cache ops out of dma-noncoherent.c 2023-11-07 09:37:42 -08:00
pageattr.c riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings 2023-11-08 07:08:33 -08:00
pgtable.c riscv: mm: Implement pmdp_collapse_flush for THP 2023-02-01 20:52:09 -08:00
physaddr.c riscv: Use PUD/P4D/PGD pages for the linear mapping 2023-04-18 20:43:04 -07:00
pmem.c RISC-V: capitalise CMO op macros 2023-11-05 09:11:23 -08:00
ptdump.c Merge patch series "Improve PTDUMP and introduce new fields" 2023-11-05 09:41:57 -08:00
tlbflush.c riscv: Improve flush_tlb_kernel_range() 2023-11-06 07:20:52 -08:00