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This patch has the goal to add support for DesignWare UFS Controller specific operations. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
37 lines
876 B
C
37 lines
876 B
C
/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _UFSHCI_DWC_H
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#define _UFSHCI_DWC_H
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/* DWC HC UFSHCI specific Registers */
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enum dwc_specific_registers {
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DWC_UFS_REG_HCLKDIV = 0xFC,
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};
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/* Clock Divider Values: Hex equivalent of frequency in MHz */
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enum clk_div_values {
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DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
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DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
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DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
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};
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/* Selector Index */
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enum selector_index {
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SELIND_LN0_TX = 0x00,
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SELIND_LN1_TX = 0x01,
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SELIND_LN0_RX = 0x04,
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SELIND_LN1_RX = 0x05,
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};
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#endif /* End of Header */
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