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801d233b73
Like the STi and sunxi series SOCs, Altera's SOCFPGA also needs a glue layer on top of the Synopsys gmac IP. This patch adds the platform driver for the glue layer which configures the IP before the generic STMMAC driver takes over. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/* Copyright Altera Corporation (C) 2014. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2,
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Adopted from dwmac-sti.c
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/stmmac.h>
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
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struct socfpga_dwmac {
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int interface;
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u32 reg_offset;
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u32 reg_shift;
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struct device *dev;
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struct regmap *sys_mgr_base_addr;
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};
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static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct regmap *sys_mgr_base_addr;
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u32 reg_offset, reg_shift;
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int ret;
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dwmac->interface = of_get_phy_mode(np);
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sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
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if (IS_ERR(sys_mgr_base_addr)) {
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dev_info(dev, "No sysmgr-syscon node found\n");
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return PTR_ERR(sys_mgr_base_addr);
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}
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ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
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if (ret) {
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dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
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return -EINVAL;
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}
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ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
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if (ret) {
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dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
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return -EINVAL;
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}
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dwmac->reg_offset = reg_offset;
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dwmac->reg_shift = reg_shift;
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dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
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dwmac->dev = dev;
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return 0;
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}
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static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
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{
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struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
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int phymode = dwmac->interface;
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u32 reg_offset = dwmac->reg_offset;
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u32 reg_shift = dwmac->reg_shift;
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u32 ctrl, val;
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switch (phymode) {
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case PHY_INTERFACE_MODE_RGMII:
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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break;
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default:
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dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
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return -EINVAL;
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}
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regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
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ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
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ctrl |= val << reg_shift;
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regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
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return 0;
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}
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static void *socfpga_dwmac_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret;
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struct socfpga_dwmac *dwmac;
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dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac)
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return ERR_PTR(-ENOMEM);
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ret = socfpga_dwmac_parse_data(dwmac, dev);
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if (ret) {
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dev_err(dev, "Unable to parse OF data\n");
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return ERR_PTR(ret);
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}
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ret = socfpga_dwmac_setup(dwmac);
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if (ret) {
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dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
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return ERR_PTR(ret);
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}
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return dwmac;
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}
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const struct stmmac_of_data socfpga_gmac_data = {
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.setup = socfpga_dwmac_probe,
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};
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