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3c1bcc8614
There are a few MAC/PHYs combinations which now support > 1Gbps. These may need to make use of link modes with bits > 31. Thus their supported PHY features or advertised features cannot be implemented using the current bitmap in a u32. Convert to using a linkmode bitmap, which can support all the currently devices link modes, and is future proof as more modes are added. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
194 lines
4.7 KiB
C
194 lines
4.7 KiB
C
/*
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* Driver for Aquantia PHY
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*
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* Author: Shaohui Xie <Shaohui.Xie@freescale.com>
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*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/mdio.h>
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#define PHY_ID_AQ1202 0x03a1b445
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#define PHY_ID_AQ2104 0x03a1b460
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#define PHY_ID_AQR105 0x03a1b4a2
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#define PHY_ID_AQR106 0x03a1b4d0
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#define PHY_ID_AQR107 0x03a1b4e0
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#define PHY_ID_AQR405 0x03a1b4b0
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static int aquantia_config_aneg(struct phy_device *phydev)
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{
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linkmode_copy(phydev->supported, phy_10gbit_features);
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linkmode_copy(phydev->advertising, phydev->supported);
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return 0;
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}
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static int aquantia_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 1);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 1);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0x1001);
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} else {
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err = phy_write_mmd(phydev, MDIO_MMD_AN, 0xd401, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff00, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xff01, 0);
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}
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return err;
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}
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static int aquantia_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xcc01);
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return (reg < 0) ? reg : 0;
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}
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static int aquantia_read_status(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (reg & MDIO_STAT1_LSTATUS)
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phydev->link = 1;
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else
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phydev->link = 0;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800);
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mdelay(10);
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reg = phy_read_mmd(phydev, MDIO_MMD_AN, 0xc800);
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switch (reg) {
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case 0x9:
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phydev->speed = SPEED_2500;
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break;
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case 0x5:
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phydev->speed = SPEED_1000;
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break;
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case 0x3:
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phydev->speed = SPEED_100;
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break;
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case 0x7:
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default:
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phydev->speed = SPEED_10000;
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break;
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}
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phydev->duplex = DUPLEX_FULL;
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return 0;
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}
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static struct phy_driver aquantia_driver[] = {
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{
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.phy_id = PHY_ID_AQ1202,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQ1202",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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{
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.phy_id = PHY_ID_AQ2104,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQ2104",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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{
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.phy_id = PHY_ID_AQR105,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQR105",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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{
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.phy_id = PHY_ID_AQR106,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQR106",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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{
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.phy_id = PHY_ID_AQR107,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQR107",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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{
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.phy_id = PHY_ID_AQR405,
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.phy_id_mask = 0xfffffff0,
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.name = "Aquantia AQR405",
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.features = PHY_10GBIT_FULL_FEATURES,
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.aneg_done = genphy_c45_aneg_done,
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.config_aneg = aquantia_config_aneg,
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.config_intr = aquantia_config_intr,
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.ack_interrupt = aquantia_ack_interrupt,
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.read_status = aquantia_read_status,
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},
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};
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module_phy_driver(aquantia_driver);
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static struct mdio_device_id __maybe_unused aquantia_tbl[] = {
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{ PHY_ID_AQ1202, 0xfffffff0 },
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{ PHY_ID_AQ2104, 0xfffffff0 },
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{ PHY_ID_AQR105, 0xfffffff0 },
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{ PHY_ID_AQR106, 0xfffffff0 },
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{ PHY_ID_AQR107, 0xfffffff0 },
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{ PHY_ID_AQR405, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, aquantia_tbl);
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MODULE_DESCRIPTION("Aquantia PHY driver");
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MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
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MODULE_LICENSE("GPL v2");
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