Grygorii Strashko 7f78322cdd phy: ti: gmii-sel: retrieve ports number and base offset from dt ... On K3 AM654x/J721E platforms the Port MII mode selection register(s) have similar format and placed in the System Control Module (SCM) module sequentially as one register per port, but, depending SOC and CPSW instance, the base offset and number of ports can be different. Hence, add possibility to retrieve number of ports and base registers offset from DT and support for max possible number of ports supported by K3 SoCs like J721E. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20200828201943.29155-4-grygorii.strashko@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2020-09-08 15:53:10 +05:30
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Kconfig	phy: ti: gmii-sel: simplify config dependencies between net drivers and gmii phy	2020-03-26 20:01:13 -07:00
Makefile	phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC	2020-01-14 10:50:19 +05:30
phy-am654-serdes.c	phy: ti: am654: update PCIe serdes config	2020-08-23 19:40:55 +05:30
phy-da8xx-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	2019-06-05 17:36:37 +02:00
phy-dm816x-usb.c	phy: ti: dm816x: remove set but unused variable	2020-07-08 16:40:24 +05:30
phy-gmii-sel.c	phy: ti: gmii-sel: retrieve ports number and base offset from dt	2020-09-08 15:53:10 +05:30
phy-j721e-wiz.c	phy: ti: j721e-wiz: Remove duplicate include	2020-08-23 21:37:28 +05:30
phy-omap-control.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
phy-omap-usb2.c	phy: omap-usb2-phy: fix coding style issues	2020-08-31 14:31:31 +05:30
phy-ti-pipe3.c	phy: ti-pipe3: remove set but unused variable	2020-07-08 16:40:28 +05:30
phy-tusb1210.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
phy-twl4030-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 61	2019-05-24 17:36:45 +02:00