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164805157f
Commit6cfcd5563b
("clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4") exposed a new issue for type2 dual mode timers on at least omap5 where the clockevent will stop when the SoC starts entering idle states during the boot. Turns out we are wrongly first enabling the system timer and then resetting it, while we must also re-enable it after reset. The current sequence leaves the timer module in a partially initialized state. This issue went unnoticed earlier with ti-sysc driver reconfiguring the timer module until we fixed the issue of ti-sysc reconfiguring system timers. Let's fix the issue by calling dmtimer_systimer_enable() from reset for both type1 and type2 timers, and switch the order of reset and enable in dmtimer_systimer_setup(). Let's also move dmtimer_systimer_enable() and dmtimer_systimer_disable() to do this without adding forward declarations. Fixes:6cfcd5563b
("clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4") Reported-by: H. Nikolaus Schaller" <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200817092428.6176-1-tony@atomide.com
756 lines
19 KiB
C
756 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/clk/clk-conf.h>
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#include <clocksource/timer-ti-dm.h>
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#include <dt-bindings/bus/ti-sysc.h>
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/* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
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#define DMTIMER_TYPE1_ENABLE ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
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SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
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#define DMTIMER_TYPE1_DISABLE (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)
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#define DMTIMER_TYPE2_ENABLE (SYSC_IDLE_SMART_WKUP << 2)
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#define DMTIMER_RESET_WAIT 100000
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#define DMTIMER_INST_DONT_CARE ~0U
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static int counter_32k;
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static u32 clocksource;
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static u32 clockevent;
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/*
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* Subset of the timer registers we use. Note that the register offsets
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* depend on the timer revision detected.
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*/
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struct dmtimer_systimer {
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void __iomem *base;
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u8 sysc;
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u8 irq_stat;
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u8 irq_ena;
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u8 pend;
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u8 load;
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u8 counter;
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u8 ctrl;
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u8 wakeup;
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u8 ifctrl;
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struct clk *fck;
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struct clk *ick;
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unsigned long rate;
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};
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struct dmtimer_clockevent {
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struct clock_event_device dev;
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struct dmtimer_systimer t;
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u32 period;
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};
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struct dmtimer_clocksource {
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struct clocksource dev;
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struct dmtimer_systimer t;
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unsigned int loadval;
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};
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/* Assumes v1 ip if bits [31:16] are zero */
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static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
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{
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u32 tidr = readl_relaxed(t->base);
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return !(tidr >> 16);
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}
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static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
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{
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u32 val;
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if (dmtimer_systimer_revision1(t))
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val = DMTIMER_TYPE1_ENABLE;
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else
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val = DMTIMER_TYPE2_ENABLE;
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writel_relaxed(val, t->base + t->sysc);
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}
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static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
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{
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if (!dmtimer_systimer_revision1(t))
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return;
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writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
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}
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static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
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{
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void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
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int ret;
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u32 l;
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dmtimer_systimer_enable(t);
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writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
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ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
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DMTIMER_RESET_WAIT);
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return ret;
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}
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/* Note we must use io_base instead of func_base for type2 OCP regs */
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static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
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{
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void __iomem *sysc = t->base + t->sysc;
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u32 l;
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dmtimer_systimer_enable(t);
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l = readl_relaxed(sysc);
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l |= BIT(0);
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writel_relaxed(l, sysc);
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return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100,
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DMTIMER_RESET_WAIT);
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}
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static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t)
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{
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int ret;
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if (dmtimer_systimer_revision1(t))
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ret = dmtimer_systimer_type1_reset(t);
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else
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ret = dmtimer_systimer_type2_reset(t);
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if (ret < 0) {
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pr_err("%s failed with %i\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id counter_match_table[] = {
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{ .compatible = "ti,omap-counter32k" },
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{ /* Sentinel */ },
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};
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/*
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* Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz
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* counter is handled by timer-ti-32k, but we need to detect it as it
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* affects the preferred dmtimer system timer configuration. There is
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* typically no use for a dmtimer clocksource if the 32 KiHz counter is
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* present, except on am437x as described below.
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*/
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static void __init dmtimer_systimer_check_counter32k(void)
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{
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struct device_node *np;
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if (counter_32k)
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return;
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np = of_find_matching_node(NULL, counter_match_table);
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if (!np) {
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counter_32k = -ENODEV;
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return;
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}
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if (of_device_is_available(np))
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counter_32k = 1;
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else
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counter_32k = -ENODEV;
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of_node_put(np);
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}
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static const struct of_device_id dmtimer_match_table[] = {
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{ .compatible = "ti,omap2420-timer", },
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{ .compatible = "ti,omap3430-timer", },
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{ .compatible = "ti,omap4430-timer", },
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{ .compatible = "ti,omap5430-timer", },
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{ .compatible = "ti,am335x-timer", },
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{ .compatible = "ti,am335x-timer-1ms", },
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{ .compatible = "ti,dm814-timer", },
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{ .compatible = "ti,dm816-timer", },
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{ /* Sentinel */ },
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};
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/*
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* Checks that system timers are configured to not reset and idle during
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* the generic timer-ti-dm device driver probe. And that the system timer
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* source clocks are properly configured. Also, let's not hog any DSP and
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* PWM capable timers unnecessarily as system timers.
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*/
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static bool __init dmtimer_is_preferred(struct device_node *np)
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{
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if (!of_device_is_available(np))
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return false;
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if (!of_property_read_bool(np->parent,
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"ti,no-reset-on-init"))
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return false;
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if (!of_property_read_bool(np->parent, "ti,no-idle"))
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return false;
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/* Secure gptimer12 is always clocked with a fixed source */
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if (!of_property_read_bool(np, "ti,timer-secure")) {
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if (!of_property_read_bool(np, "assigned-clocks"))
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return false;
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if (!of_property_read_bool(np, "assigned-clock-parents"))
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return false;
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}
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if (of_property_read_bool(np, "ti,timer-dsp"))
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return false;
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if (of_property_read_bool(np, "ti,timer-pwm"))
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return false;
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return true;
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}
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/*
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* Finds the first available usable always-on timer, and assigns it to either
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* clockevent or clocksource depending if the counter_32k is available on the
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* SoC or not.
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*
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* Some omap3 boards with unreliable oscillator must not use the counter_32k
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* or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable
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* oscillator should really set counter_32k as disabled, and delete dmtimer1
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* ti,always-on property, but let's not count on it. For these quirky cases,
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* we prefer using the always-on secure dmtimer12 with the internal 32 KiHz
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* clock as the clocksource, and any available dmtimer as clockevent.
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*
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* For am437x, we are using am335x style dmtimer clocksource. It is unclear
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* if this quirk handling is really needed, but let's change it separately
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* based on testing as it might cause side effects.
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*/
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static void __init dmtimer_systimer_assign_alwon(void)
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{
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struct device_node *np;
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u32 pa = 0;
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bool quirk_unreliable_oscillator = false;
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/* Quirk unreliable 32 KiHz oscillator with incomplete dts */
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if (of_machine_is_compatible("ti,omap3-beagle") ||
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of_machine_is_compatible("timll,omap3-devkit8000")) {
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quirk_unreliable_oscillator = true;
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counter_32k = -ENODEV;
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}
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/* Quirk am437x using am335x style dmtimer clocksource */
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if (of_machine_is_compatible("ti,am43"))
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counter_32k = -ENODEV;
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for_each_matching_node(np, dmtimer_match_table) {
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if (!dmtimer_is_preferred(np))
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continue;
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if (of_property_read_bool(np, "ti,timer-alwon")) {
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const __be32 *addr;
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addr = of_get_address(np, 0, NULL, NULL);
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pa = of_translate_address(np, addr);
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if (pa) {
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/* Quirky omap3 boards must use dmtimer12 */
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if (quirk_unreliable_oscillator &&
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pa == 0x48318000)
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continue;
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of_node_put(np);
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break;
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}
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}
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}
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/* Usually no need for dmtimer clocksource if we have counter32 */
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if (counter_32k >= 0) {
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clockevent = pa;
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clocksource = 0;
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} else {
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clocksource = pa;
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clockevent = DMTIMER_INST_DONT_CARE;
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}
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}
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/* Finds the first usable dmtimer, used for the don't care case */
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static u32 __init dmtimer_systimer_find_first_available(void)
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{
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struct device_node *np;
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const __be32 *addr;
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u32 pa = 0;
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for_each_matching_node(np, dmtimer_match_table) {
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if (!dmtimer_is_preferred(np))
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continue;
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addr = of_get_address(np, 0, NULL, NULL);
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pa = of_translate_address(np, addr);
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if (pa) {
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if (pa == clocksource || pa == clockevent) {
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pa = 0;
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continue;
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}
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of_node_put(np);
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break;
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}
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}
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return pa;
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}
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/* Selects the best clocksource and clockevent to use */
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static void __init dmtimer_systimer_select_best(void)
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{
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dmtimer_systimer_check_counter32k();
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dmtimer_systimer_assign_alwon();
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if (clockevent == DMTIMER_INST_DONT_CARE)
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clockevent = dmtimer_systimer_find_first_available();
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pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n",
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__func__, counter_32k, clocksource, clockevent);
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}
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/* Interface clocks are only available on some SoCs variants */
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static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t,
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struct device_node *np,
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const char *name,
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unsigned long *rate)
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{
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struct clk *clock;
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unsigned long r;
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bool is_ick = false;
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int error;
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is_ick = !strncmp(name, "ick", 3);
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clock = of_clk_get_by_name(np, name);
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if ((PTR_ERR(clock) == -EINVAL) && is_ick)
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return 0;
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else if (IS_ERR(clock))
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return PTR_ERR(clock);
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error = clk_prepare_enable(clock);
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if (error)
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return error;
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r = clk_get_rate(clock);
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if (!r)
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return -ENODEV;
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if (is_ick)
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t->ick = clock;
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else
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t->fck = clock;
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*rate = r;
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return 0;
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}
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static int __init dmtimer_systimer_setup(struct device_node *np,
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struct dmtimer_systimer *t)
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{
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unsigned long rate;
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u8 regbase;
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int error;
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if (!of_device_is_compatible(np->parent, "ti,sysc"))
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return -EINVAL;
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t->base = of_iomap(np, 0);
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if (!t->base)
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return -ENXIO;
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/*
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* Enable optional assigned-clock-parents configured at the timer
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* node level. For regular device drivers, this is done automatically
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* by bus related code such as platform_drv_probe().
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*/
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error = of_clk_set_defaults(np, false);
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if (error < 0)
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pr_err("%s: clock source init failed: %i\n", __func__, error);
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/* For ti-sysc, we have timer clocks at the parent module level */
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error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate);
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if (error)
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goto err_unmap;
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t->rate = rate;
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error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate);
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if (error)
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goto err_unmap;
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if (dmtimer_systimer_revision1(t)) {
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t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
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t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
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t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET;
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regbase = 0;
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} else {
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t->irq_stat = OMAP_TIMER_V2_IRQSTATUS;
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t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET;
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regbase = OMAP_TIMER_V2_FUNC_OFFSET;
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t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET;
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}
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t->sysc = OMAP_TIMER_OCP_CFG_OFFSET;
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t->load = regbase + _OMAP_TIMER_LOAD_OFFSET;
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t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET;
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t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET;
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t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
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t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
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dmtimer_systimer_reset(t);
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dmtimer_systimer_enable(t);
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pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
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readl_relaxed(t->base + t->sysc));
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return 0;
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err_unmap:
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iounmap(t->base);
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return error;
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}
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/* Clockevent */
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static struct dmtimer_clockevent *
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to_dmtimer_clockevent(struct clock_event_device *clockevent)
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{
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return container_of(clockevent, struct dmtimer_clockevent, dev);
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}
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static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data)
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{
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struct dmtimer_clockevent *clkevt = data;
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struct dmtimer_systimer *t = &clkevt->t;
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writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
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clkevt->dev.event_handler(&clkevt->dev);
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return IRQ_HANDLED;
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}
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static int dmtimer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
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struct dmtimer_systimer *t = &clkevt->t;
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void __iomem *pend = t->base + t->pend;
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writel_relaxed(0xffffffff - cycles, t->base + t->counter);
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while (readl_relaxed(pend) & WP_TCRR)
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cpu_relax();
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writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
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while (readl_relaxed(pend) & WP_TCLR)
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cpu_relax();
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return 0;
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}
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static int dmtimer_clockevent_shutdown(struct clock_event_device *evt)
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{
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struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
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struct dmtimer_systimer *t = &clkevt->t;
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void __iomem *ctrl = t->base + t->ctrl;
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u32 l;
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l = readl_relaxed(ctrl);
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if (l & OMAP_TIMER_CTRL_ST) {
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l &= ~BIT(0);
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writel_relaxed(l, ctrl);
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/* Flush posted write */
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l = readl_relaxed(ctrl);
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/* Wait for functional clock period x 3.5 */
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udelay(3500000 / t->rate + 1);
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}
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writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dmtimer_set_periodic(struct clock_event_device *evt)
|
|
{
|
|
struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
|
|
struct dmtimer_systimer *t = &clkevt->t;
|
|
void __iomem *pend = t->base + t->pend;
|
|
|
|
dmtimer_clockevent_shutdown(evt);
|
|
|
|
/* Looks like we need to first set the load value separately */
|
|
writel_relaxed(clkevt->period, t->base + t->load);
|
|
while (readl_relaxed(pend) & WP_TLDR)
|
|
cpu_relax();
|
|
|
|
writel_relaxed(clkevt->period, t->base + t->counter);
|
|
while (readl_relaxed(pend) & WP_TCRR)
|
|
cpu_relax();
|
|
|
|
writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
|
|
t->base + t->ctrl);
|
|
while (readl_relaxed(pend) & WP_TCLR)
|
|
cpu_relax();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_clockevent_idle(struct clock_event_device *evt)
|
|
{
|
|
struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
|
|
struct dmtimer_systimer *t = &clkevt->t;
|
|
|
|
dmtimer_systimer_disable(t);
|
|
clk_disable(t->fck);
|
|
}
|
|
|
|
static void omap_clockevent_unidle(struct clock_event_device *evt)
|
|
{
|
|
struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
|
|
struct dmtimer_systimer *t = &clkevt->t;
|
|
int error;
|
|
|
|
error = clk_enable(t->fck);
|
|
if (error)
|
|
pr_err("could not enable timer fck on resume: %i\n", error);
|
|
|
|
dmtimer_systimer_enable(t);
|
|
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
|
|
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
|
|
}
|
|
|
|
static int __init dmtimer_clockevent_init(struct device_node *np)
|
|
{
|
|
struct dmtimer_clockevent *clkevt;
|
|
struct clock_event_device *dev;
|
|
struct dmtimer_systimer *t;
|
|
int error;
|
|
|
|
clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
|
|
if (!clkevt)
|
|
return -ENOMEM;
|
|
|
|
t = &clkevt->t;
|
|
dev = &clkevt->dev;
|
|
|
|
/*
|
|
* We mostly use cpuidle_coupled with ARM local timers for runtime,
|
|
* so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here.
|
|
*/
|
|
dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
|
dev->rating = 300;
|
|
dev->set_next_event = dmtimer_set_next_event;
|
|
dev->set_state_shutdown = dmtimer_clockevent_shutdown;
|
|
dev->set_state_periodic = dmtimer_set_periodic;
|
|
dev->set_state_oneshot = dmtimer_clockevent_shutdown;
|
|
dev->tick_resume = dmtimer_clockevent_shutdown;
|
|
dev->cpumask = cpu_possible_mask;
|
|
|
|
dev->irq = irq_of_parse_and_map(np, 0);
|
|
if (!dev->irq) {
|
|
error = -ENXIO;
|
|
goto err_out_free;
|
|
}
|
|
|
|
error = dmtimer_systimer_setup(np, &clkevt->t);
|
|
if (error)
|
|
goto err_out_free;
|
|
|
|
clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ);
|
|
|
|
/*
|
|
* For clock-event timers we never read the timer counter and
|
|
* so we are not impacted by errata i103 and i767. Therefore,
|
|
* we can safely ignore this errata for clock-event timers.
|
|
*/
|
|
writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
|
|
|
|
error = request_irq(dev->irq, dmtimer_clockevent_interrupt,
|
|
IRQF_TIMER, "clockevent", clkevt);
|
|
if (error)
|
|
goto err_out_unmap;
|
|
|
|
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
|
|
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
|
|
|
|
pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n",
|
|
of_find_property(np, "ti,timer-alwon", NULL) ?
|
|
"always-on " : "", t->rate, np->parent);
|
|
|
|
clockevents_config_and_register(dev, t->rate,
|
|
3, /* Timer internal resynch latency */
|
|
0xffffffff);
|
|
|
|
if (of_machine_is_compatible("ti,am33xx") ||
|
|
of_machine_is_compatible("ti,am43")) {
|
|
dev->suspend = omap_clockevent_idle;
|
|
dev->resume = omap_clockevent_unidle;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out_unmap:
|
|
iounmap(t->base);
|
|
|
|
err_out_free:
|
|
kfree(clkevt);
|
|
|
|
return error;
|
|
}
|
|
|
|
/* Clocksource */
|
|
static struct dmtimer_clocksource *
|
|
to_dmtimer_clocksource(struct clocksource *cs)
|
|
{
|
|
return container_of(cs, struct dmtimer_clocksource, dev);
|
|
}
|
|
|
|
static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs)
|
|
{
|
|
struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
|
|
struct dmtimer_systimer *t = &clksrc->t;
|
|
|
|
return (u64)readl_relaxed(t->base + t->counter);
|
|
}
|
|
|
|
static void __iomem *dmtimer_sched_clock_counter;
|
|
|
|
static u64 notrace dmtimer_read_sched_clock(void)
|
|
{
|
|
return readl_relaxed(dmtimer_sched_clock_counter);
|
|
}
|
|
|
|
static void dmtimer_clocksource_suspend(struct clocksource *cs)
|
|
{
|
|
struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
|
|
struct dmtimer_systimer *t = &clksrc->t;
|
|
|
|
clksrc->loadval = readl_relaxed(t->base + t->counter);
|
|
dmtimer_systimer_disable(t);
|
|
clk_disable(t->fck);
|
|
}
|
|
|
|
static void dmtimer_clocksource_resume(struct clocksource *cs)
|
|
{
|
|
struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
|
|
struct dmtimer_systimer *t = &clksrc->t;
|
|
int error;
|
|
|
|
error = clk_enable(t->fck);
|
|
if (error)
|
|
pr_err("could not enable timer fck on resume: %i\n", error);
|
|
|
|
dmtimer_systimer_enable(t);
|
|
writel_relaxed(clksrc->loadval, t->base + t->counter);
|
|
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
|
|
t->base + t->ctrl);
|
|
}
|
|
|
|
static int __init dmtimer_clocksource_init(struct device_node *np)
|
|
{
|
|
struct dmtimer_clocksource *clksrc;
|
|
struct dmtimer_systimer *t;
|
|
struct clocksource *dev;
|
|
int error;
|
|
|
|
clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
|
|
if (!clksrc)
|
|
return -ENOMEM;
|
|
|
|
dev = &clksrc->dev;
|
|
t = &clksrc->t;
|
|
|
|
error = dmtimer_systimer_setup(np, t);
|
|
if (error)
|
|
goto err_out_free;
|
|
|
|
dev->name = "dmtimer";
|
|
dev->rating = 300;
|
|
dev->read = dmtimer_clocksource_read_cycles;
|
|
dev->mask = CLOCKSOURCE_MASK(32);
|
|
dev->flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
|
|
|
/* Unlike for clockevent, legacy code sets suspend only for am4 */
|
|
if (of_machine_is_compatible("ti,am43")) {
|
|
dev->suspend = dmtimer_clocksource_suspend;
|
|
dev->resume = dmtimer_clocksource_resume;
|
|
}
|
|
|
|
writel_relaxed(0, t->base + t->counter);
|
|
writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
|
|
t->base + t->ctrl);
|
|
|
|
pr_info("TI gptimer clocksource: %s%pOF\n",
|
|
of_find_property(np, "ti,timer-alwon", NULL) ?
|
|
"always-on " : "", np->parent);
|
|
|
|
if (!dmtimer_sched_clock_counter) {
|
|
dmtimer_sched_clock_counter = t->base + t->counter;
|
|
sched_clock_register(dmtimer_read_sched_clock, 32, t->rate);
|
|
}
|
|
|
|
if (clocksource_register_hz(dev, t->rate))
|
|
pr_err("Could not register clocksource %pOF\n", np);
|
|
|
|
return 0;
|
|
|
|
err_out_free:
|
|
kfree(clksrc);
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* To detect between a clocksource and clockevent, we assume the device tree
|
|
* has no interrupts configured for a clocksource timer.
|
|
*/
|
|
static int __init dmtimer_systimer_init(struct device_node *np)
|
|
{
|
|
const __be32 *addr;
|
|
u32 pa;
|
|
|
|
/* One time init for the preferred timer configuration */
|
|
if (!clocksource && !clockevent)
|
|
dmtimer_systimer_select_best();
|
|
|
|
if (!clocksource && !clockevent) {
|
|
pr_err("%s: unable to detect system timers, update dtb?\n",
|
|
__func__);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr = of_get_address(np, 0, NULL, NULL);
|
|
pa = of_translate_address(np, addr);
|
|
if (!pa)
|
|
return -EINVAL;
|
|
|
|
if (counter_32k <= 0 && clocksource == pa)
|
|
return dmtimer_clocksource_init(np);
|
|
|
|
if (clockevent == pa)
|
|
return dmtimer_clockevent_init(np);
|
|
|
|
return 0;
|
|
}
|
|
|
|
TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init);
|
|
TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init);
|