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1abd350237
Robert Jarzmik reports that his PXA25x system fails to boot with 4.12, failing at __flush_whole_cache in arch/arm/mm/proc-xscale.S:215: 0xc0019e20 <+0>: ldr r1, [pc, #788] 0xc0019e24 <+4>: ldr r0, [r1] <== here with r1 containing 0xc06f82cd, which is the address of "clean_addr". Examination of the System.map shows: c06f22c8 D user_pmd_table c06f22cc d __warned.19178 c06f22cd d clean_addr indicating that a .data.unlikely section has appeared just before the .data section from proc-xscale.S. According to objdump -h, it appears that our assembly files default their .data alignment to 2**0, which is bad news if the preceding .data section size is not power-of-2 aligned at link time. Add the appropriate .align directives to all assembly files in arch/arm that are missing them where we require an appropriate alignment. Reported-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
263 lines
6.2 KiB
ArmAsm
263 lines
6.2 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-v4wb.S
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*
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* The total size of the data cache.
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*/
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#if defined(CONFIG_CPU_SA110)
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# define CACHE_DSIZE 16384
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#elif defined(CONFIG_CPU_SA1100)
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# define CACHE_DSIZE 8192
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#else
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# error Unknown cache size
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#endif
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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* cache line maintenance instructions.
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*
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* Size Clean (ticks) Dirty (ticks)
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* 4096 21 20 21 53 55 54
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* 8192 40 41 40 106 100 102
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* 16384 77 77 76 140 140 138
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* 32768 150 149 150 214 216 212 <---
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* 65536 296 297 296 351 358 361
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* 131072 591 591 591 656 657 651
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* Whole 132 136 132 221 217 207 <---
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*/
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#define CACHE_DLIMIT (CACHE_DSIZE * 4)
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.data
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.align 2
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flush_base:
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.long FLUSH_BASE
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.text
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(v4wb_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(v4wb_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(v4wb_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v4wb_flush_kern_cache_all)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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__flush_whole_cache:
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ldr r3, =flush_base
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ldr r1, [r3, #0]
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eor r1, r1, #CACHE_DSIZE
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str r1, [r3, #0]
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add r2, r1, #CACHE_DSIZE
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1: ldr r3, [r1], #32
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cmp r1, r2
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blo 1b
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#ifdef FLUSH_BASE_MINICACHE
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add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
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sub r1, r2, #512 @ only 512 bytes
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1: ldr r3, [r1], #32
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cmp r1, r2
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blo 1b
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive, page aligned)
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* - end - end address (exclusive, page aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4wb_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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tst r2, #VM_EXEC @ executable region?
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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cmp r3, #CACHE_DLIMIT @ total size >= limit?
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bhs __flush_whole_cache @ flush whole D cache
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v4wb_flush_kern_dcache_area)
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add r1, r0, r1
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/* fall through */
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_coherent_kern_range)
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/* fall through */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4wb_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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v4wb_dma_inv_range:
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean (write back) the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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v4wb_dma_clean_range:
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* This is actually the same as v4wb_coherent_kern_range()
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*/
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.globl v4wb_dma_flush_range
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.set v4wb_dma_flush_range, v4wb_coherent_kern_range
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4wb_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq v4wb_dma_clean_range
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bcs v4wb_dma_inv_range
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b v4wb_dma_flush_range
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ENDPROC(v4wb_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4wb_dma_unmap_area)
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ret lr
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ENDPROC(v4wb_dma_unmap_area)
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.globl v4wb_flush_kern_cache_louis
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.equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v4wb
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