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2a0c28063d
The zoran driver can be moved back to mainline after it has been converted by Corentin Labbe to vb2. Note that the zoran driver no longer supports video output, but video capture is working fine now. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
204 lines
5.1 KiB
C
204 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Zoran ZR36060 basic configuration functions - header file
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*
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* Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
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*/
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#ifndef ZR36060_H
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#define ZR36060_H
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#include "videocodec.h"
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/* data stored for each zoran jpeg codec chip */
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struct zr36060 {
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char name[32];
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int num;
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/* io datastructure */
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struct videocodec *codec;
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// last coder status
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__u8 status;
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// actual coder setup
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int mode;
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__u16 width;
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__u16 height;
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__u16 bitrate_ctrl;
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__u32 total_code_vol;
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__u32 real_code_vol;
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__u16 max_block_vol;
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__u8 h_samp_ratio[8];
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__u8 v_samp_ratio[8];
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__u16 scalefact;
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__u16 dri;
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/* app/com marker data */
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struct jpeg_app_marker app;
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struct jpeg_com_marker com;
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};
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/* ZR36060 register addresses */
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#define ZR060_LOAD 0x000
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#define ZR060_CFSR 0x001
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#define ZR060_CIR 0x002
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#define ZR060_CMR 0x003
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#define ZR060_MBZ 0x004
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#define ZR060_MBCVR 0x005
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#define ZR060_MER 0x006
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#define ZR060_IMR 0x007
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#define ZR060_ISR 0x008
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#define ZR060_TCV_NET_HI 0x009
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#define ZR060_TCV_NET_MH 0x00a
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#define ZR060_TCV_NET_ML 0x00b
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#define ZR060_TCV_NET_LO 0x00c
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#define ZR060_TCV_DATA_HI 0x00d
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#define ZR060_TCV_DATA_MH 0x00e
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#define ZR060_TCV_DATA_ML 0x00f
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#define ZR060_TCV_DATA_LO 0x010
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#define ZR060_SF_HI 0x011
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#define ZR060_SF_LO 0x012
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#define ZR060_AF_HI 0x013
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#define ZR060_AF_M 0x014
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#define ZR060_AF_LO 0x015
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#define ZR060_ACV_HI 0x016
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#define ZR060_ACV_MH 0x017
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#define ZR060_ACV_ML 0x018
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#define ZR060_ACV_LO 0x019
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#define ZR060_ACT_HI 0x01a
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#define ZR060_ACT_MH 0x01b
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#define ZR060_ACT_ML 0x01c
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#define ZR060_ACT_LO 0x01d
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#define ZR060_ACV_TURN_HI 0x01e
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#define ZR060_ACV_TURN_MH 0x01f
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#define ZR060_ACV_TURN_ML 0x020
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#define ZR060_ACV_TURN_LO 0x021
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#define ZR060_IDR_DEV 0x022
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#define ZR060_IDR_REV 0x023
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#define ZR060_TCR_HI 0x024
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#define ZR060_TCR_LO 0x025
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#define ZR060_VCR 0x030
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#define ZR060_VPR 0x031
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#define ZR060_SR 0x032
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#define ZR060_BCR_Y 0x033
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#define ZR060_BCR_U 0x034
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#define ZR060_BCR_V 0x035
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#define ZR060_SGR_VTOTAL_HI 0x036
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#define ZR060_SGR_VTOTAL_LO 0x037
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#define ZR060_SGR_HTOTAL_HI 0x038
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#define ZR060_SGR_HTOTAL_LO 0x039
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#define ZR060_SGR_VSYNC 0x03a
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#define ZR060_SGR_HSYNC 0x03b
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#define ZR060_SGR_BVSTART 0x03c
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#define ZR060_SGR_BHSTART 0x03d
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#define ZR060_SGR_BVEND_HI 0x03e
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#define ZR060_SGR_BVEND_LO 0x03f
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#define ZR060_SGR_BHEND_HI 0x040
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#define ZR060_SGR_BHEND_LO 0x041
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#define ZR060_AAR_VSTART_HI 0x042
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#define ZR060_AAR_VSTART_LO 0x043
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#define ZR060_AAR_VEND_HI 0x044
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#define ZR060_AAR_VEND_LO 0x045
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#define ZR060_AAR_HSTART_HI 0x046
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#define ZR060_AAR_HSTART_LO 0x047
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#define ZR060_AAR_HEND_HI 0x048
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#define ZR060_AAR_HEND_LO 0x049
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#define ZR060_SWR_VSTART_HI 0x04a
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#define ZR060_SWR_VSTART_LO 0x04b
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#define ZR060_SWR_VEND_HI 0x04c
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#define ZR060_SWR_VEND_LO 0x04d
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#define ZR060_SWR_HSTART_HI 0x04e
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#define ZR060_SWR_HSTART_LO 0x04f
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#define ZR060_SWR_HEND_HI 0x050
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#define ZR060_SWR_HEND_LO 0x051
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#define ZR060_SOF_IDX 0x060
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#define ZR060_SOS_IDX 0x07a
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#define ZR060_DRI_IDX 0x0c0
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#define ZR060_DQT_IDX 0x0cc
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#define ZR060_DHT_IDX 0x1d4
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#define ZR060_APP_IDX 0x380
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#define ZR060_COM_IDX 0x3c0
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/* ZR36060 LOAD register bits */
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#define ZR060_LOAD_LOAD BIT(7)
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#define ZR060_LOAD_SYNC_RST BIT(0)
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/* ZR36060 Code FIFO Status register bits */
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#define ZR060_CFSR_BUSY BIT(7)
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#define ZR060_CFSR_C_BUSY BIT(2)
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#define ZR060_CFSR_CFIFO (3 << 0)
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/* ZR36060 Code Interface register */
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#define ZR060_CIR_CODE16 BIT(7)
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#define ZR060_CIR_ENDIAN BIT(6)
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#define ZR060_CIR_CFIS BIT(2)
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#define ZR060_CIR_CODE_MSTR BIT(0)
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/* ZR36060 Codec Mode register */
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#define ZR060_CMR_COMP BIT(7)
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#define ZR060_CMR_ATP BIT(6)
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#define ZR060_CMR_PASS2 BIT(5)
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#define ZR060_CMR_TLM BIT(4)
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#define ZR060_CMR_BRB BIT(2)
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#define ZR060_CMR_FSF BIT(1)
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/* ZR36060 Markers Enable register */
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#define ZR060_MER_APP BIT(7)
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#define ZR060_MER_COM BIT(6)
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#define ZR060_MER_DRI BIT(5)
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#define ZR060_MER_DQT BIT(4)
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#define ZR060_MER_DHT BIT(3)
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/* ZR36060 Interrupt Mask register */
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#define ZR060_IMR_EOAV BIT(3)
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#define ZR060_IMR_EOI BIT(2)
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#define ZR060_IMR_END BIT(1)
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#define ZR060_IMR_DATA_ERR BIT(0)
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/* ZR36060 Interrupt Status register */
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#define ZR060_ISR_PRO_CNT (3 << 6)
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#define ZR060_ISR_EOAV BIT(3)
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#define ZR060_ISR_EOI BIT(2)
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#define ZR060_ISR_END BIT(1)
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#define ZR060_ISR_DATA_ERR BIT(0)
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/* ZR36060 Video Control register */
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#define ZR060_VCR_VIDEO8 BIT(7)
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#define ZR060_VCR_RANGE BIT(6)
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#define ZR060_VCR_FI_DET BIT(3)
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#define ZR060_VCR_FI_VEDGE BIT(2)
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#define ZR060_VCR_FI_EXT BIT(1)
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#define ZR060_VCR_SYNC_MSTR BIT(0)
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/* ZR36060 Video Polarity register */
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#define ZR060_VPR_VCLK_POL BIT(7)
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#define ZR060_VPR_P_VAL_POL BIT(6)
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#define ZR060_VPR_POE_POL BIT(5)
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#define ZR060_VPR_S_IMG_POL BIT(4)
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#define ZR060_VPR_BL_POL BIT(3)
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#define ZR060_VPR_FI_POL BIT(2)
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#define ZR060_VPR_HS_POL BIT(1)
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#define ZR060_VPR_VS_POL BIT(0)
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/* ZR36060 Scaling register */
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#define ZR060_SR_V_SCALE BIT(2)
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#define ZR060_SR_H_SCALE2 BIT(0)
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#define ZR060_SR_H_SCALE4 (2 << 0)
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int zr36060_init_module(void);
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void zr36060_cleanup_module(void);
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#endif /*fndef ZR36060_H */
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