Lad Prabhakar 7dd48e96d0 riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} ... IRQC support for RZ/Five is still missing so drop the interrupts and interrupt-parent properties from the PHY nodes of ETH{0,1}. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230102222708.274369-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>		2023-01-26 16:02:16 +01:00
..
dts	riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1}	2023-01-26 16:02:16 +01:00
.gitignore	riscv: efi: enable generic EFI compressed boot	2022-09-20 09:50:30 +02:00
install.sh	kbuild: factor out the common installation code into scripts/install.sh	2022-05-11 21:45:53 +09:00
loader.lds.S	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
loader.S	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00
Makefile	riscv: boot: add zstd support	2022-12-08 16:44:42 -08:00