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439057ec3b
LoongArch maintains cache coherency in hardware, but its WUC attribute (Weak-ordered UnCached, which is similar to WC) is out of the scope of cache coherency machanism. This means WUC can only used for write-only memory regions. Cc: Daniel Vetter <daniel@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/**************************************************************************
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*
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* Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
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* Jerome Glisse
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pgtable.h>
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <drm/drm_sysfs.h>
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#include <drm/ttm/ttm_caching.h>
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#include "ttm_module.h"
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/**
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* DOC: TTM
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*
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* TTM is a memory manager for accelerator devices with dedicated memory.
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*
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* The basic idea is that resources are grouped together in buffer objects of
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* certain size and TTM handles lifetime, movement and CPU mappings of those
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* objects.
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*
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* TODO: Add more design background and information here.
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*/
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/**
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* ttm_prot_from_caching - Modify the page protection according to the
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* ttm cacing mode
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* @caching: The ttm caching mode
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* @tmp: The original page protection
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*
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* Return: The modified page protection
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*/
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pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
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{
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/* Cached mappings need no adjustment */
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if (caching == ttm_cached)
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return tmp;
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#if defined(__i386__) || defined(__x86_64__)
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if (caching == ttm_write_combined)
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tmp = pgprot_writecombine(tmp);
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#ifndef CONFIG_UML
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else if (boot_cpu_data.x86 > 3)
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tmp = pgprot_noncached(tmp);
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#endif /* CONFIG_UML */
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#endif /* __i386__ || __x86_64__ */
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#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
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defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
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if (caching == ttm_write_combined)
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tmp = pgprot_writecombine(tmp);
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else
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tmp = pgprot_noncached(tmp);
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#endif
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#if defined(__sparc__)
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tmp = pgprot_noncached(tmp);
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#endif
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return tmp;
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}
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MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse");
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MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)");
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MODULE_LICENSE("GPL and additional rights");
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