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There are times that we need to know which controller we are on to decide how to exclude devices properly. We now pass the pci_controller that we are going to use down to the pci_exclude_device function. This will greatly simplify being able to exclude the PHBs in multiple controller setups. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* Support for indirect PCI bridges.
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*
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* Copyright (C) 1998 Gabriel Paubert.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#ifdef CONFIG_PPC_INDIRECT_PCI_BE
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#define PCI_CFG_OUT out_be32
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#else
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#define PCI_CFG_OUT out_le32
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#endif
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static int
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indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | ((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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*val = in_8(cfg_data);
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break;
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case 2:
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*val = in_le16(cfg_data);
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break;
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default:
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*val = in_le32(cfg_data);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | ((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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out_8(cfg_data, val);
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break;
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case 2:
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out_le16(cfg_data, val);
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break;
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default:
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out_le32(cfg_data, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops indirect_pci_ops =
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{
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indirect_read_config,
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indirect_write_config
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};
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void __init
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setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
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void __iomem * cfg_data)
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{
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hose->cfg_addr = cfg_addr;
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hose->cfg_data = cfg_data;
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hose->ops = &indirect_pci_ops;
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}
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void __init
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setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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{
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unsigned long base = cfg_addr & PAGE_MASK;
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void __iomem *mbase, *addr, *data;
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mbase = ioremap(base, PAGE_SIZE);
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addr = mbase + (cfg_addr & ~PAGE_MASK);
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if ((cfg_data & PAGE_MASK) != base)
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mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
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data = mbase + (cfg_data & ~PAGE_MASK);
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setup_indirect_pci_nomap(hose, addr, data);
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}
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