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fe364a7d95
Intel Elkhart Lake PSE DMA implementation is integrated with crossbar IP in order to serve more hardware than there are DMA request lines available. Due to this, program xBAR hardware to make flexible support of PSE peripheral. The Device-to-Device has not been tested and it's not supported by DMA Engine, but it's left in the code for the sake of documenting hardware features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210712113940.42753-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2013,2018,2020-2021 Intel Corporation
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#include <linux/bitops.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "internal.h"
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#define DMA_CTL_CH(x) (0x1000 + (x) * 4)
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#define DMA_SRC_ADDR_FILLIN(x) (0x1100 + (x) * 4)
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#define DMA_DST_ADDR_FILLIN(x) (0x1200 + (x) * 4)
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#define DMA_XBAR_SEL(x) (0x1300 + (x) * 4)
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#define DMA_REGACCESS_CHID_CFG (0x1400)
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#define CTL_CH_TRANSFER_MODE_MASK GENMASK(1, 0)
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#define CTL_CH_TRANSFER_MODE_S2S 0
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#define CTL_CH_TRANSFER_MODE_S2D 1
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#define CTL_CH_TRANSFER_MODE_D2S 2
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#define CTL_CH_TRANSFER_MODE_D2D 3
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#define CTL_CH_RD_RS_MASK GENMASK(4, 3)
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#define CTL_CH_WR_RS_MASK GENMASK(6, 5)
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#define CTL_CH_RD_NON_SNOOP_BIT BIT(8)
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#define CTL_CH_WR_NON_SNOOP_BIT BIT(9)
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#define XBAR_SEL_DEVID_MASK GENMASK(15, 0)
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#define XBAR_SEL_RX_TX_BIT BIT(16)
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#define XBAR_SEL_RX_TX_SHIFT 16
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#define REGACCESS_CHID_MASK GENMASK(2, 0)
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static unsigned int idma32_get_slave_devfn(struct dw_dma_chan *dwc)
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{
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struct device *slave = dwc->chan.slave;
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if (!slave || !dev_is_pci(slave))
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return 0;
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return to_pci_dev(slave)->devfn;
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}
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static void idma32_initialize_chan_xbar(struct dw_dma_chan *dwc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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void __iomem *misc = __dw_regs(dw);
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u32 cfghi = 0, cfglo = 0;
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u8 dst_id, src_id;
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u32 value;
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/* DMA Channel ID Configuration register must be programmed first */
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value = readl(misc + DMA_REGACCESS_CHID_CFG);
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value &= ~REGACCESS_CHID_MASK;
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value |= dwc->chan.chan_id;
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writel(value, misc + DMA_REGACCESS_CHID_CFG);
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/* Configure channel attributes */
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value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id));
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value &= ~(CTL_CH_RD_NON_SNOOP_BIT | CTL_CH_WR_NON_SNOOP_BIT);
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value &= ~(CTL_CH_RD_RS_MASK | CTL_CH_WR_RS_MASK);
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value &= ~CTL_CH_TRANSFER_MODE_MASK;
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switch (dwc->direction) {
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case DMA_MEM_TO_DEV:
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value |= CTL_CH_TRANSFER_MODE_D2S;
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value |= CTL_CH_WR_NON_SNOOP_BIT;
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break;
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case DMA_DEV_TO_MEM:
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value |= CTL_CH_TRANSFER_MODE_S2D;
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value |= CTL_CH_RD_NON_SNOOP_BIT;
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break;
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default:
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/*
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* Memory-to-Memory and Device-to-Device are ignored for now.
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*
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* For Memory-to-Memory transfers we would need to set mode
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* and disable snooping on both sides.
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*/
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return;
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}
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writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id));
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/* Configure crossbar selection */
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value = readl(misc + DMA_XBAR_SEL(dwc->chan.chan_id));
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/* DEVFN selection */
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value &= ~XBAR_SEL_DEVID_MASK;
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value |= idma32_get_slave_devfn(dwc);
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switch (dwc->direction) {
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case DMA_MEM_TO_DEV:
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value |= XBAR_SEL_RX_TX_BIT;
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break;
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case DMA_DEV_TO_MEM:
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value &= ~XBAR_SEL_RX_TX_BIT;
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break;
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default:
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/* Memory-to-Memory and Device-to-Device are ignored for now */
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return;
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}
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writel(value, misc + DMA_XBAR_SEL(dwc->chan.chan_id));
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/* Configure DMA channel low and high registers */
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switch (dwc->direction) {
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case DMA_MEM_TO_DEV:
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dst_id = dwc->chan.chan_id;
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src_id = dwc->dws.src_id;
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break;
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case DMA_DEV_TO_MEM:
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dst_id = dwc->dws.dst_id;
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src_id = dwc->chan.chan_id;
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break;
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default:
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/* Memory-to-Memory and Device-to-Device are ignored for now */
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return;
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}
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/* Set default burst alignment */
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cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
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/* Low 4 bits of the request lines */
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cfghi |= IDMA32C_CFGH_DST_PER(dst_id & 0xf);
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cfghi |= IDMA32C_CFGH_SRC_PER(src_id & 0xf);
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/* Request line extension (2 bits) */
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cfghi |= IDMA32C_CFGH_DST_PER_EXT(dst_id >> 4 & 0x3);
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cfghi |= IDMA32C_CFGH_SRC_PER_EXT(src_id >> 4 & 0x3);
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channel_writel(dwc, CFG_LO, cfglo);
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channel_writel(dwc, CFG_HI, cfghi);
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}
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static void idma32_initialize_chan_generic(struct dw_dma_chan *dwc)
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{
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u32 cfghi = 0;
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u32 cfglo = 0;
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/* Set default burst alignment */
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cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
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/* Low 4 bits of the request lines */
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cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
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cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
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/* Request line extension (2 bits) */
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cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
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cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
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channel_writel(dwc, CFG_LO, cfglo);
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channel_writel(dwc, CFG_HI, cfghi);
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}
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static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
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{
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u32 cfglo = channel_readl(dwc, CFG_LO);
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if (drain)
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cfglo |= IDMA32C_CFGL_CH_DRAIN;
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channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
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}
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static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
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{
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u32 cfglo = channel_readl(dwc, CFG_LO);
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if (drain)
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cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
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channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
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}
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static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
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size_t bytes, unsigned int width, size_t *len)
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{
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u32 block;
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if (bytes > dwc->block_size) {
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block = dwc->block_size;
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*len = dwc->block_size;
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} else {
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block = bytes;
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*len = bytes;
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}
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return block;
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}
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static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
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{
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return IDMA32C_CTLH_BLOCK_TS(block);
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}
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static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
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{
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struct dma_slave_config *sconfig = &dwc->dma_sconfig;
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u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
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u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
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return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
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DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
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}
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static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
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{
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*maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
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}
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static void idma32_set_device_name(struct dw_dma *dw, int id)
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{
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snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
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}
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/*
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* Program FIFO size of channels.
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*
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* By default full FIFO (512 bytes) is assigned to channel 0. Here we
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* slice FIFO on equal parts between channels.
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*/
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static void idma32_fifo_partition(struct dw_dma *dw)
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{
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u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
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IDMA32C_FP_UPDATE;
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u64 fifo_partition = 0;
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/* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
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fifo_partition |= value << 0;
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/* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
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fifo_partition |= value << 32;
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/* Program FIFO Partition registers - 64 bytes per channel */
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idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
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idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
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}
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static void idma32_disable(struct dw_dma *dw)
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{
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do_dw_dma_off(dw);
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idma32_fifo_partition(dw);
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}
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static void idma32_enable(struct dw_dma *dw)
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{
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idma32_fifo_partition(dw);
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do_dw_dma_on(dw);
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}
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int idma32_dma_probe(struct dw_dma_chip *chip)
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{
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struct dw_dma *dw;
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dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
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if (!dw)
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return -ENOMEM;
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/* Channel operations */
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if (chip->pdata->quirks & DW_DMA_QUIRK_XBAR_PRESENT)
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dw->initialize_chan = idma32_initialize_chan_xbar;
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else
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dw->initialize_chan = idma32_initialize_chan_generic;
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dw->suspend_chan = idma32_suspend_chan;
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dw->resume_chan = idma32_resume_chan;
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dw->prepare_ctllo = idma32_prepare_ctllo;
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dw->encode_maxburst = idma32_encode_maxburst;
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dw->bytes2block = idma32_bytes2block;
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dw->block2bytes = idma32_block2bytes;
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/* Device operations */
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dw->set_device_name = idma32_set_device_name;
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dw->disable = idma32_disable;
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dw->enable = idma32_enable;
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chip->dw = dw;
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return do_dma_probe(chip);
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}
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EXPORT_SYMBOL_GPL(idma32_dma_probe);
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int idma32_dma_remove(struct dw_dma_chip *chip)
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{
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return do_dma_remove(chip);
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}
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EXPORT_SYMBOL_GPL(idma32_dma_remove);
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