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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 only as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details to obtain the license point your browser to http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 12 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081202.028166291@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* drxd_firm.h
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*
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* Copyright (C) 2006-2007 Micronas
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*/
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#ifndef _DRXD_FIRM_H_
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#define _DRXD_FIRM_H_
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#include <linux/types.h>
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#include "drxd_map_firm.h"
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#define VERSION_MAJOR 1
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#define VERSION_MINOR 4
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#define VERSION_PATCH 23
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#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
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#define DRXD_MAX_RETRIES (1000)
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#define HI_I2C_DELAY 84
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#define HI_I2C_BRIDGE_DELAY 750
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#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
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#define EQ_TD_TPS_PWR_QPSK 0x016a
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#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
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#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
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#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
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#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
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#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
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#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
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#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
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#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
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#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
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#define DRXD_DEF_AG_PWD_PRO 0x0000
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#define DRXD_DEF_AG_AGC_SIO 0x0000
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#define DRXD_FE_CTRL_MAX 1023
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#define DRXD_OSCDEV_DO_SCAN (16)
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#define DRXD_OSCDEV_DONT_SCAN (0)
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#define DRXD_OSCDEV_STEP (275)
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#define DRXD_SCAN_TIMEOUT (650)
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#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
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#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
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#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
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#define IRLEN_COARSE_8K (10)
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#define IRLEN_FINE_8K (10)
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#define IRLEN_COARSE_2K (7)
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#define IRLEN_FINE_2K (9)
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#define DIFF_INVALID (511)
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#define DIFF_TARGET (4)
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#define DIFF_MARGIN (1)
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extern u8 DRXD_InitAtomicRead[];
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extern u8 DRXD_HiI2cPatch_1[];
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extern u8 DRXD_HiI2cPatch_3[];
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extern u8 DRXD_InitSC[];
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extern u8 DRXD_ResetCEFR[];
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extern u8 DRXD_InitFEA2_1[];
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extern u8 DRXD_InitFEA2_2[];
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extern u8 DRXD_InitCPA2[];
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extern u8 DRXD_InitCEA2[];
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extern u8 DRXD_InitEQA2[];
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extern u8 DRXD_InitECA2[];
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extern u8 DRXD_ResetECA2[];
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extern u8 DRXD_ResetECRAM[];
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extern u8 DRXD_A2_microcode[];
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extern u32 DRXD_A2_microcode_length;
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extern u8 DRXD_InitFEB1_1[];
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extern u8 DRXD_InitFEB1_2[];
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extern u8 DRXD_InitCPB1[];
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extern u8 DRXD_InitCEB1[];
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extern u8 DRXD_InitEQB1[];
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extern u8 DRXD_InitECB1[];
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extern u8 DRXD_InitDiversityFront[];
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extern u8 DRXD_InitDiversityEnd[];
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extern u8 DRXD_DisableDiversity[];
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extern u8 DRXD_StartDiversityFront[];
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extern u8 DRXD_StartDiversityEnd[];
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extern u8 DRXD_DiversityDelay8MHZ[];
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extern u8 DRXD_DiversityDelay6MHZ[];
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extern u8 DRXD_B1_microcode[];
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extern u32 DRXD_B1_microcode_length;
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#endif
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