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26fb751ca3
Currently, SBI APIs accept a hartmask that is generated from struct cpumask. Cpumask data structure can hold upto NR_CPUs value. Thus, it is not the correct data structure for hartids as it can be higher than NR_CPUs for platforms with sparse or discontguous hartids. Remove all association between hartid mask and struct cpumask. Reviewed-by: Anup Patel <anup@brainfault.org> (For Linux RISC-V changes) Acked-by: Anup Patel <anup@brainfault.org> (For KVM RISC-V changes) Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/sbi.h>
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#include <asm/kvm_vcpu_timer.h>
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#include <asm/kvm_vcpu_sbi.h>
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static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
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unsigned long *out_val,
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struct kvm_cpu_trap *utrap, bool *exit)
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{
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int ret = 0;
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struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
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u64 next_cycle;
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if (cp->a6 != SBI_EXT_TIME_SET_TIMER)
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return -EINVAL;
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#if __riscv_xlen == 32
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next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0;
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#else
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next_cycle = (u64)cp->a0;
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#endif
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kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle);
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return ret;
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}
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const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time = {
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.extid_start = SBI_EXT_TIME,
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.extid_end = SBI_EXT_TIME,
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.handler = kvm_sbi_ext_time_handler,
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};
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static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
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unsigned long *out_val,
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struct kvm_cpu_trap *utrap, bool *exit)
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{
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int ret = 0;
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unsigned long i;
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struct kvm_vcpu *tmp;
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struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
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unsigned long hmask = cp->a0;
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unsigned long hbase = cp->a1;
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if (cp->a6 != SBI_EXT_IPI_SEND_IPI)
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return -EINVAL;
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kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
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if (hbase != -1UL) {
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if (tmp->vcpu_id < hbase)
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continue;
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if (!(hmask & (1UL << (tmp->vcpu_id - hbase))))
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continue;
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}
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ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT);
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if (ret < 0)
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break;
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}
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return ret;
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}
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const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi = {
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.extid_start = SBI_EXT_IPI,
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.extid_end = SBI_EXT_IPI,
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.handler = kvm_sbi_ext_ipi_handler,
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};
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static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
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unsigned long *out_val,
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struct kvm_cpu_trap *utrap, bool *exit)
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{
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int ret = 0;
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unsigned long i;
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struct cpumask cm;
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struct kvm_vcpu *tmp;
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struct kvm_cpu_context *cp = &vcpu->arch.guest_context;
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unsigned long hmask = cp->a0;
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unsigned long hbase = cp->a1;
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unsigned long funcid = cp->a6;
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cpumask_clear(&cm);
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kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
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if (hbase != -1UL) {
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if (tmp->vcpu_id < hbase)
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continue;
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if (!(hmask & (1UL << (tmp->vcpu_id - hbase))))
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continue;
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}
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if (tmp->cpu < 0)
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continue;
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cpumask_set_cpu(tmp->cpu, &cm);
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}
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switch (funcid) {
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case SBI_EXT_RFENCE_REMOTE_FENCE_I:
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ret = sbi_remote_fence_i(&cm);
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break;
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case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
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ret = sbi_remote_hfence_vvma(&cm, cp->a2, cp->a3);
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break;
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case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
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ret = sbi_remote_hfence_vvma_asid(&cm, cp->a2,
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cp->a3, cp->a4);
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break;
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case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
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case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
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case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
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case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
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/* TODO: implement for nested hypervisor case */
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default:
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ret = -EOPNOTSUPP;
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}
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return ret;
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}
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const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence = {
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.extid_start = SBI_EXT_RFENCE,
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.extid_end = SBI_EXT_RFENCE,
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.handler = kvm_sbi_ext_rfence_handler,
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};
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