Radhey Shyam Pandey 7bcdaa6581 dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit ... AXIDMA IP in SG mode sets completion bit to 1 when the transfer is completed. Read this bit to move descriptor from active list to the done list. This feature is needed when interrupt delay timeout and IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing interrupt threshold. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-6-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2023-08-21 18:40:37 +05:30
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Makefile	dmaengine: xilinx: xdma: Add xilinx xdma driver	2023-02-10 11:32:26 +05:30
xdma-regs.h	dmaengine: xilinx: xdma: Add xilinx xdma driver	2023-02-10 11:32:26 +05:30
xdma.c	dmaengine: xilinx: xdma: Fix some kernel-doc comments	2023-03-17 23:23:07 +05:30
xilinx_dma.c	dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit	2023-08-21 18:40:37 +05:30
xilinx_dpdma.c	dmaengine: xilinx: use strscpy to replace strlcpy	2022-07-21 19:04:35 +05:30
zynqmp_dma.c	dmaengine: Explicitly include correct DT includes	2023-08-01 23:51:27 +05:30