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dd7b2f035e
On 64-bit CPUs with no-execute support and non-snooping icache, such as
970 or POWER4, we have a software mechanism to ensure coherency of the
cache (using exec faults when needed).
This was broken due to a logic error when the code was rewritten
from assembly to C, previously the assembly code did:
BEGIN_FTR_SECTION
mr r4,r30
mr r5,r7
bl hash_page_do_lazy_icache
END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
Which tests that:
(cpu_features & (NOEXECUTE | COHERENT_ICACHE)) == NOEXECUTE
Which says that the current cpu does have NOEXECUTE, but does not have
COHERENT_ICACHE.
Fixes: 91f1da9979 ("powerpc/mm: Convert 4k hash insert to C")
Fixes: 89ff725051 ("powerpc/mm: Convert __hash_page_64K to C")
Fixes: a43c0eb836 ("powerpc/mm: Convert 4k insert from asm to C")
Cc: stable@vger.kernel.org # v4.5+
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[mpe: Change log verbosification]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
332 lines
9.1 KiB
C
332 lines
9.1 KiB
C
/*
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* Copyright IBM Corporation, 2015
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* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU Lesser General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#include <linux/mm.h>
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#include <asm/machdep.h>
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#include <asm/mmu.h>
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/*
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* index from 0 - 15
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*/
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bool __rpte_sub_valid(real_pte_t rpte, unsigned long index)
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{
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unsigned long g_idx;
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unsigned long ptev = pte_val(rpte.pte);
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g_idx = (ptev & H_PAGE_COMBO_VALID) >> H_PAGE_F_GIX_SHIFT;
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index = index >> 2;
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if (g_idx & (0x1 << index))
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return true;
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else
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return false;
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}
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/*
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* index from 0 - 15
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*/
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static unsigned long mark_subptegroup_valid(unsigned long ptev, unsigned long index)
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{
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unsigned long g_idx;
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if (!(ptev & H_PAGE_COMBO))
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return ptev;
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index = index >> 2;
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g_idx = 0x1 << index;
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return ptev | (g_idx << H_PAGE_F_GIX_SHIFT);
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}
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int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
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pte_t *ptep, unsigned long trap, unsigned long flags,
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int ssize, int subpg_prot)
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{
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real_pte_t rpte;
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unsigned long *hidxp;
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unsigned long hpte_group;
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unsigned int subpg_index;
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unsigned long rflags, pa, hidx;
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unsigned long old_pte, new_pte, subpg_pte;
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unsigned long vpn, hash, slot;
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unsigned long shift = mmu_psize_defs[MMU_PAGE_4K].shift;
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/*
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* atomically mark the linux large page PTE busy and dirty
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*/
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do {
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pte_t pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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/* If PTE busy, retry the access */
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if (unlikely(old_pte & H_PAGE_BUSY))
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return 0;
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/* If PTE permissions don't match, take page fault */
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if (unlikely(!check_pte_access(access, old_pte)))
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return 1;
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/*
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* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access. Since this is 4K insert of 64K page size
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* also add H_PAGE_COMBO
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*/
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new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED | H_PAGE_COMBO;
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if (access & _PAGE_WRITE)
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new_pte |= _PAGE_DIRTY;
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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/*
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* Handle the subpage protection bits
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*/
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subpg_pte = new_pte & ~subpg_prot;
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rflags = htab_convert_pte_flags(subpg_pte);
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if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
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!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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/*
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* No CPU has hugepages but lacks no execute, so we
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* don't need to worry about that case
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*/
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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}
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subpg_index = (ea & (PAGE_SIZE - 1)) >> shift;
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vpn = hpt_vpn(ea, vsid, ssize);
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rpte = __real_pte(__pte(old_pte), ptep);
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/*
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*None of the sub 4k page is hashed
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*/
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if (!(old_pte & H_PAGE_HASHPTE))
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goto htab_insert_hpte;
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/*
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* Check if the pte was already inserted into the hash table
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* as a 64k HW page, and invalidate the 64k HPTE if so.
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*/
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if (!(old_pte & H_PAGE_COMBO)) {
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flush_hash_page(vpn, rpte, MMU_PAGE_64K, ssize, flags);
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/*
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* clear the old slot details from the old and new pte.
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* On hash insert failure we use old pte value and we don't
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* want slot information there if we have a insert failure.
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*/
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old_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);
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new_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);
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goto htab_insert_hpte;
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}
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/*
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* Check for sub page valid and update
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*/
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if (__rpte_sub_valid(rpte, subpg_index)) {
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int ret;
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hash = hpt_hash(vpn, shift, ssize);
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hidx = __rpte_to_hidx(rpte, subpg_index);
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if (hidx & _PTEIDX_SECONDARY)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += hidx & _PTEIDX_GROUP_IX;
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ret = mmu_hash_ops.hpte_updatepp(slot, rflags, vpn,
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MMU_PAGE_4K, MMU_PAGE_4K,
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ssize, flags);
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/*
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*if we failed because typically the HPTE wasn't really here
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* we try an insertion.
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*/
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if (ret == -1)
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goto htab_insert_hpte;
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*ptep = __pte(new_pte & ~H_PAGE_BUSY);
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return 0;
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}
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htab_insert_hpte:
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/*
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* handle H_PAGE_4K_PFN case
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*/
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if (old_pte & H_PAGE_4K_PFN) {
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/*
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* All the sub 4k page have the same
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* physical address.
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*/
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pa = pte_pfn(__pte(old_pte)) << HW_PAGE_SHIFT;
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} else {
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
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pa += (subpg_index << shift);
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}
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hash = hpt_hash(vpn, shift, ssize);
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repeat:
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hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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/* Insert into the hash table, primary slot */
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slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 0,
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MMU_PAGE_4K, MMU_PAGE_4K, ssize);
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/*
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* Primary is full, try the secondary
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*/
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if (unlikely(slot == -1)) {
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hpte_group = ((~hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa,
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rflags, HPTE_V_SECONDARY,
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MMU_PAGE_4K, MMU_PAGE_4K,
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ssize);
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if (slot == -1) {
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if (mftb() & 0x1)
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hpte_group = ((hash & htab_hash_mask) *
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HPTES_PER_GROUP) & ~0x7UL;
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mmu_hash_ops.hpte_remove(hpte_group);
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/*
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* FIXME!! Should be try the group from which we removed ?
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*/
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goto repeat;
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}
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}
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/*
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* Hypervisor failure. Restore old pte and return -1
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* similar to __hash_page_*
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*/
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if (unlikely(slot == -2)) {
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*ptep = __pte(old_pte);
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hash_failure_debug(ea, access, vsid, trap, ssize,
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MMU_PAGE_4K, MMU_PAGE_4K, old_pte);
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return -1;
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}
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/*
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* Insert slot number & secondary bit in PTE second half,
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* clear H_PAGE_BUSY and set appropriate HPTE slot bit
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* Since we have H_PAGE_BUSY set on ptep, we can be sure
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* nobody is undating hidx.
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*/
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hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
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rpte.hidx &= ~(0xfUL << (subpg_index << 2));
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*hidxp = rpte.hidx | (slot << (subpg_index << 2));
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new_pte = mark_subptegroup_valid(new_pte, subpg_index);
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new_pte |= H_PAGE_HASHPTE;
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/*
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* check __real_pte for details on matching smp_rmb()
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*/
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smp_wmb();
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*ptep = __pte(new_pte & ~H_PAGE_BUSY);
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return 0;
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}
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int __hash_page_64K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned long flags, int ssize)
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{
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unsigned long hpte_group;
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unsigned long rflags, pa;
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unsigned long old_pte, new_pte;
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unsigned long vpn, hash, slot;
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unsigned long shift = mmu_psize_defs[MMU_PAGE_64K].shift;
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/*
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* atomically mark the linux large page PTE busy and dirty
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*/
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do {
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pte_t pte = READ_ONCE(*ptep);
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old_pte = pte_val(pte);
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/* If PTE busy, retry the access */
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if (unlikely(old_pte & H_PAGE_BUSY))
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return 0;
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/* If PTE permissions don't match, take page fault */
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if (unlikely(!check_pte_access(access, old_pte)))
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return 1;
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/*
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* Check if PTE has the cache-inhibit bit set
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* If so, bail out and refault as a 4k page
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*/
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if (!mmu_has_feature(MMU_FTR_CI_LARGE_PAGE) &&
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unlikely(pte_ci(pte)))
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return 0;
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/*
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* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access.
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*/
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new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED;
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if (access & _PAGE_WRITE)
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new_pte |= _PAGE_DIRTY;
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} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
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rflags = htab_convert_pte_flags(new_pte);
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if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
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!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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vpn = hpt_vpn(ea, vsid, ssize);
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if (unlikely(old_pte & H_PAGE_HASHPTE)) {
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/*
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* There MIGHT be an HPTE for this pte
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*/
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hash = hpt_hash(vpn, shift, ssize);
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if (old_pte & H_PAGE_F_SECOND)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;
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if (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_64K,
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MMU_PAGE_64K, ssize,
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flags) == -1)
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old_pte &= ~_PAGE_HPTEFLAGS;
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}
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if (likely(!(old_pte & H_PAGE_HASHPTE))) {
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
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hash = hpt_hash(vpn, shift, ssize);
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repeat:
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hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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/* Insert into the hash table, primary slot */
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slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, 0,
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MMU_PAGE_64K, MMU_PAGE_64K,
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ssize);
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/*
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* Primary is full, try the secondary
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*/
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if (unlikely(slot == -1)) {
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hpte_group = ((~hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
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slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa,
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rflags,
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HPTE_V_SECONDARY,
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MMU_PAGE_64K,
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MMU_PAGE_64K, ssize);
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if (slot == -1) {
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if (mftb() & 0x1)
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hpte_group = ((hash & htab_hash_mask) *
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HPTES_PER_GROUP) & ~0x7UL;
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mmu_hash_ops.hpte_remove(hpte_group);
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/*
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* FIXME!! Should be try the group from which we removed ?
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*/
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goto repeat;
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}
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}
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/*
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* Hypervisor failure. Restore old pte and return -1
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* similar to __hash_page_*
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*/
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if (unlikely(slot == -2)) {
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*ptep = __pte(old_pte);
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hash_failure_debug(ea, access, vsid, trap, ssize,
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MMU_PAGE_64K, MMU_PAGE_64K, old_pte);
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return -1;
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}
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new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
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new_pte |= (slot << H_PAGE_F_GIX_SHIFT) &
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(H_PAGE_F_SECOND | H_PAGE_F_GIX);
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}
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*ptep = __pte(new_pte & ~H_PAGE_BUSY);
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return 0;
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}
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