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Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
18 lines
557 B
C
18 lines
557 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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#endif
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