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79f3c37c88
Assign proper FIMC-IS UART gate clock in the device DT node and not
use the SRC_MASK gate. This fixes regression introduced in commit
a37c82a3b3 ("clk: samsung: exynos4: Remove
SRC_MASK_ISP gates").
Without this change exynos4 fimc-is driver fails to probe with an
error log:
[ 1.842447] ERROR: could not get clock /camera/fimc-is@12000000:uart(13)
[ 1.848529] exynos4-fimc-is 12000000.fimc-is: failed to get clock: uart
[ 1.855275] exynos4-fimc-is: probe of 12000000.fimc-is failed with error -2
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
287 lines
7.4 KiB
Plaintext
287 lines
7.4 KiB
Plaintext
/*
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* Samsung's Exynos4x12 SoCs device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos4.dtsi"
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#include "exynos4x12-pinctrl.dtsi"
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/ {
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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fimc-lite0 = &fimc_lite_0;
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fimc-lite1 = &fimc_lite_1;
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mshc0 = &mshc_0;
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x40000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@2f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x2f000 0x1000>;
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};
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};
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pd_isp: isp-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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#power-domain-cells = <0>;
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};
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4412-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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mct@10050000 {
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compatible = "samsung,exynos4412-mct";
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reg = <0x10050000 0x800>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 57 0>,
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<1 &combiner 12 5>,
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<2 &combiner 12 6>,
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<3 &combiner 12 7>,
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<4 &gic 1 12 0>;
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};
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};
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combiner: interrupt-controller@10440000 {
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
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<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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adc: adc@126C0000 {
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compatible = "samsung,exynos-adc-v1";
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reg = <0x126C0000 0x100>;
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interrupt-parent = <&combiner>;
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interrupts = <10 3>;
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clocks = <&clock CLK_TSADC>;
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clock-names = "adc";
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#io-channel-cells = <1>;
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io-channel-ranges;
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samsung,syscon-phandle = <&pmu_system_controller>;
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status = "disabled";
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <10 0>;
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};
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pinctrl_3: pinctrl@106E0000 {
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compatible = "samsung,exynos4x12-pinctrl";
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reg = <0x106E0000 0x1000>;
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interrupts = <0 72 0>;
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};
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pmu_system_controller: system-controller@10020000 {
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compatible = "samsung,exynos4212-pmu", "syscon";
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clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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"clkout4", "clkout8", "clkout9";
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clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
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<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
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<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
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<&clock CLK_XUSBXTI>;
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#clock-cells = <1>;
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};
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g2d@10800000 {
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compatible = "samsung,exynos4212-g2d";
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reg = <0x10800000 0x1000>;
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interrupts = <0 89 0>;
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clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
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clock-names = "sclk_fimg2d", "fimg2d";
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status = "disabled";
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};
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camera {
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clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
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<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
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clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
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fimc_0: fimc@11800000 {
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compatible = "samsung,exynos4212-fimc";
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,isp-wb;
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samsung,cam-if;
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};
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fimc_1: fimc@11810000 {
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compatible = "samsung,exynos4212-fimc";
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,isp-wb;
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samsung,cam-if;
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};
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fimc_2: fimc@11820000 {
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compatible = "samsung,exynos4212-fimc";
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samsung,pix-limits = <4224 8192 1920 4224>;
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samsung,mainscaler-ext;
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samsung,isp-wb;
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samsung,lcd-wb;
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samsung,cam-if;
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};
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fimc_3: fimc@11830000 {
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compatible = "samsung,exynos4212-fimc";
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samsung,pix-limits = <1920 8192 1366 1920>;
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samsung,rotators = <0>;
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samsung,mainscaler-ext;
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samsung,isp-wb;
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samsung,lcd-wb;
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};
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fimc_lite_0: fimc-lite@12390000 {
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compatible = "samsung,exynos4212-fimc-lite";
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reg = <0x12390000 0x1000>;
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interrupts = <0 105 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE0>;
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clock-names = "flite";
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status = "disabled";
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};
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fimc_lite_1: fimc-lite@123A0000 {
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compatible = "samsung,exynos4212-fimc-lite";
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reg = <0x123A0000 0x1000>;
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interrupts = <0 106 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE1>;
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clock-names = "flite";
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status = "disabled";
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};
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fimc_is: fimc-is@12000000 {
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compatible = "samsung,exynos4212-fimc-is", "simple-bus";
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reg = <0x12000000 0x260000>;
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interrupts = <0 90 0>, <0 95 0>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_FIMC_LITE0>,
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<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
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<&clock CLK_PPMUISPMX>,
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<&clock CLK_MOUT_MPLL_USER_T>,
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<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
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<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
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<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
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<&clock CLK_DIV_MCUISP0>,
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<&clock CLK_DIV_MCUISP1>,
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<&clock CLK_UART_ISP_SCLK>,
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<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
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<&clock CLK_ACLK400_MCUISP>,
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<&clock CLK_DIV_ACLK400_MCUISP>;
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clock-names = "lite0", "lite1", "ppmuispx",
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"ppmuispmx", "mpll", "isp",
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"drc", "fd", "mcuisp",
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"ispdiv0", "ispdiv1", "mcuispdiv0",
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"mcuispdiv1", "uart", "aclk200",
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"div_aclk200", "aclk400mcuisp",
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"div_aclk400mcuisp";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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pmu {
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reg = <0x10020000 0x3000>;
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};
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i2c1_isp: i2c-isp@12140000 {
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compatible = "samsung,exynos4212-i2c-isp";
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reg = <0x12140000 0x100>;
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clocks = <&clock CLK_I2C1_ISP>;
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clock-names = "i2c_isp";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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mshc_0: mmc@12550000 {
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compatible = "samsung,exynos4412-dw-mshc";
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reg = <0x12550000 0x1000>;
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-depth = <0x80>;
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clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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exynos-usbphy@125B0000 {
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compatible = "samsung,exynos4x12-usb2-phy";
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samsung,sysreg-phandle = <&sys_reg>;
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};
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tmu@100C0000 {
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compatible = "samsung,exynos4412-tmu";
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interrupt-parent = <&combiner>;
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interrupts = <2 4>;
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reg = <0x100C0000 0x100>;
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clocks = <&clock 383>;
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clock-names = "tmu_apbif";
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status = "disabled";
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};
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};
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