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7973b1d7bf
Now that we have driver support for the basic clocks, add them to the dtsi and update existing peripherals. Also add reset controls to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
423 lines
10 KiB
Plaintext
423 lines
10 KiB
Plaintext
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this library; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "skeleton64.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &r_uart;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x3>;
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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memory {
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/* 8GB max. with LPAE */
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reg = <0 0x20000000 0x02 0>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* map 64 bit address range down to 32 bits,
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* as the peripherals are all under 512MB.
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*/
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ranges = <0 0 0 0x20000000>;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll4: clk@0600000c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x0600000c 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll12: clk@0600002c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-pll4-clk";
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reg = <0x0600002c 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll12";
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};
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gt_clk: clk@0600005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-gt-clk";
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reg = <0x0600005c 0x4>;
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clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "gt";
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};
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ahb0: clk@06000060 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000060 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb0";
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};
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ahb1: clk@06000064 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000064 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb1";
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};
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ahb2: clk@06000068 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-ahb-clk";
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reg = <0x06000068 0x4>;
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clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "ahb2";
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};
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apb0: clk@06000070 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-apb0-clk";
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reg = <0x06000070 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "apb0";
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};
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apb1: clk@06000074 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-apb1-clk";
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reg = <0x06000074 0x4>;
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clocks = <&osc24M>, <&pll4>;
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clock-output-names = "apb1";
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};
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cci400_clk: clk@06000078 {
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#clock-cells = <0>;
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compatible = "allwinner,sun9i-a80-gt-clk";
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reg = <0x06000078 0x4>;
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clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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clock-output-names = "cci400";
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};
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ahb0_gates: clk@06000580 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
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reg = <0x06000580 0x4>;
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clocks = <&ahb0>;
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clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
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"ahb0_ss", "ahb0_sd", "ahb0_nand1",
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"ahb0_nand0", "ahb0_sdram",
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"ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
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"ahb0_spi0","ahb0_spi1", "ahb0_spi2",
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"ahb0_spi3";
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};
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ahb1_gates: clk@06000584 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
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reg = <0x06000584 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
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"ahb1_gmac", "ahb1_msgbox",
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"ahb1_spinlock", "ahb1_hstimer",
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"ahb1_dma";
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};
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ahb2_gates: clk@06000588 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
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reg = <0x06000588 0x4>;
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clocks = <&ahb2>;
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clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
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"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
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"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
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};
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apb0_gates: clk@06000590 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-apb0-gates-clk";
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reg = <0x06000590 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_spdif", "apb0_pio",
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"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
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"apb0_lradc", "apb0_gpadc", "apb0_twd",
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"apb0_cirtx";
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};
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apb1_gates: clk@06000594 {
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#clock-cells = <1>;
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compatible = "allwinner,sun9i-a80-apb1-gates-clk";
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reg = <0x06000594 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
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"apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* map 64 bit address range down to 32 bits,
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* as the peripherals are all under 512MB.
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*/
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ranges = <0 0 0 0x20000000>;
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gic: interrupt-controller@01c41000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c41000 0x1000>,
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<0x01c42000 0x1000>,
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<0x01c44000 0x2000>,
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<0x01c46000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 0xf04>;
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};
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ahb0_resets: reset@060005a0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x060005a0 0x4>;
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};
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ahb1_resets: reset@060005a4 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x060005a4 0x4>;
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};
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ahb2_resets: reset@060005a8 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x060005a8 0x4>;
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};
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apb0_resets: reset@060005b0 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x060005b0 0x4>;
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};
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apb1_resets: reset@060005b4 {
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-clock-reset";
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reg = <0x060005b4 0x4>;
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};
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timer@06000c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x06000c00 0xa0>;
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interrupts = <0 18 4>,
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<0 19 4>,
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<0 20 4>,
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<0 21 4>,
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<0 22 4>,
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<0 23 4>;
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clocks = <&osc24M>;
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};
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uart0: serial@07000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07000000 0x400>;
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interrupts = <0 0 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 16>;
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resets = <&apb1_resets 16>;
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status = "disabled";
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};
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uart1: serial@07000400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07000400 0x400>;
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interrupts = <0 1 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 17>;
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resets = <&apb1_resets 17>;
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status = "disabled";
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};
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uart2: serial@07000800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07000800 0x400>;
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interrupts = <0 2 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 18>;
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resets = <&apb1_resets 18>;
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status = "disabled";
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};
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uart3: serial@07000c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07000c00 0x400>;
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interrupts = <0 3 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 19>;
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resets = <&apb1_resets 19>;
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status = "disabled";
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};
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uart4: serial@07001000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07001000 0x400>;
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interrupts = <0 4 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 20>;
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resets = <&apb1_resets 20>;
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status = "disabled";
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};
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uart5: serial@07001400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x07001400 0x400>;
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interrupts = <0 5 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 21>;
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resets = <&apb1_resets 21>;
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status = "disabled";
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};
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r_wdt: watchdog@08001000 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x08001000 0x20>;
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interrupts = <0 36 4>;
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};
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r_uart: serial@08002800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x08002800 0x400>;
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interrupts = <0 38 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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};
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};
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