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06e26b75f5
platform_irq_count() and platform_get_irq() is the more generic way (independent of device trees) to determine the count of available interrupts. So use this instead. As platform_irq_count() might return an error code (which of_irq_count doesn't) some additional handling is necessary. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1576672860-14420-1-git-send-email-peng.fan@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1188 lines
31 KiB
C
1188 lines
31 KiB
C
/*
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* Marvell 37xx SoC pinctrl driver
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*
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* Copyright (C) 2017 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2 or later. This program is licensed "as is"
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* without any warranty of any kind, whether express or implied.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "../pinctrl-utils.h"
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#define OUTPUT_EN 0x0
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#define INPUT_VAL 0x10
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#define OUTPUT_VAL 0x18
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#define OUTPUT_CTL 0x20
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#define SELECTION 0x30
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#define IRQ_EN 0x0
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#define IRQ_POL 0x08
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#define IRQ_STATUS 0x10
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#define IRQ_WKUP 0x18
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#define NB_FUNCS 3
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#define GPIO_PER_REG 32
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/**
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* struct armada_37xx_pin_group: represents group of pins of a pinmux function.
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* The pins of a pinmux groups are composed of one or two groups of contiguous
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* pins.
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* @name: Name of the pin group, used to lookup the group.
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* @start_pins: Index of the first pin of the main range of pins belonging to
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* the group
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* @npins: Number of pins included in the first range
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* @reg_mask: Bit mask matching the group in the selection register
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* @extra_pins: Index of the first pin of the optional second range of pins
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* belonging to the group
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* @npins: Number of pins included in the second optional range
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* @funcs: A list of pinmux functions that can be selected for this group.
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* @pins: List of the pins included in the group
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*/
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struct armada_37xx_pin_group {
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const char *name;
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unsigned int start_pin;
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unsigned int npins;
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u32 reg_mask;
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u32 val[NB_FUNCS];
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unsigned int extra_pin;
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unsigned int extra_npins;
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const char *funcs[NB_FUNCS];
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unsigned int *pins;
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};
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struct armada_37xx_pin_data {
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u8 nr_pins;
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char *name;
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struct armada_37xx_pin_group *groups;
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int ngroups;
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};
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struct armada_37xx_pmx_func {
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const char *name;
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const char **groups;
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unsigned int ngroups;
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};
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struct armada_37xx_pm_state {
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u32 out_en_l;
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u32 out_en_h;
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u32 out_val_l;
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u32 out_val_h;
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u32 irq_en_l;
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u32 irq_en_h;
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u32 irq_pol_l;
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u32 irq_pol_h;
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u32 selection;
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};
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struct armada_37xx_pinctrl {
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struct regmap *regmap;
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void __iomem *base;
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const struct armada_37xx_pin_data *data;
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struct device *dev;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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spinlock_t irq_lock;
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struct pinctrl_desc pctl;
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struct pinctrl_dev *pctl_dev;
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struct armada_37xx_pin_group *groups;
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unsigned int ngroups;
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struct armada_37xx_pmx_func *funcs;
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unsigned int nfuncs;
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struct armada_37xx_pm_state pm;
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};
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#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {0, _mask}, \
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.funcs = {_func1, _func2} \
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}
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#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {0, _mask}, \
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.funcs = {_func1, "gpio"} \
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}
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#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_val1, _val2}, \
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.funcs = {_func1, "gpio"} \
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}
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#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_v1, _v2, _v3}, \
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.funcs = {_f1, _f2, "gpio"} \
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}
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#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
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_f1, _f2) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_v1, _v2}, \
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.extra_pin = _start2, \
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.extra_npins = _nr2, \
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.funcs = {_f1, _f2} \
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}
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static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
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PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
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PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
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PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
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PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
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PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
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PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
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PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
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PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
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PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
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PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
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PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
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PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
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PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
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PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
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PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
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PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
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PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
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PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
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BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
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18, 2, "gpio", "uart"),
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PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
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PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
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PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
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PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
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};
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static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
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PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
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PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
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PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
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PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
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PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
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PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
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PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
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PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
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PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
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PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
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PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
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PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
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"mii", "mii_err"),
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};
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static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
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.nr_pins = 36,
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.name = "GPIO1",
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.groups = armada_37xx_nb_groups,
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.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
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};
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static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
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.nr_pins = 30,
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.name = "GPIO2",
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.groups = armada_37xx_sb_groups,
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.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
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};
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static inline void armada_37xx_update_reg(unsigned int *reg,
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unsigned int *offset)
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{
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/* We never have more than 2 registers */
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if (*offset >= GPIO_PER_REG) {
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*offset -= GPIO_PER_REG;
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*reg += sizeof(u32);
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}
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}
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static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
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struct armada_37xx_pinctrl *info, int pin, int *grp)
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{
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while (*grp < info->ngroups) {
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struct armada_37xx_pin_group *group = &info->groups[*grp];
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int j;
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*grp = *grp + 1;
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for (j = 0; j < (group->npins + group->extra_npins); j++)
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if (group->pins[j] == pin)
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return group;
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}
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return NULL;
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}
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static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned long *config)
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{
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return -ENOTSUPP;
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}
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static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned long *configs,
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unsigned int num_configs)
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{
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return -ENOTSUPP;
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}
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static const struct pinconf_ops armada_37xx_pinconf_ops = {
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.is_generic = true,
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.pin_config_group_get = armada_37xx_pin_config_group_get,
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.pin_config_group_set = armada_37xx_pin_config_group_set,
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};
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static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->ngroups;
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}
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static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->groups[group].name;
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}
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static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const unsigned int **pins,
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unsigned int *npins)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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if (selector >= info->ngroups)
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return -EINVAL;
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*pins = info->groups[selector].pins;
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*npins = info->groups[selector].npins +
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info->groups[selector].extra_npins;
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return 0;
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}
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static const struct pinctrl_ops armada_37xx_pctrl_ops = {
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.get_groups_count = armada_37xx_get_groups_count,
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.get_group_name = armada_37xx_get_group_name,
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.get_group_pins = armada_37xx_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_free_map = pinctrl_utils_free_map,
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};
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/*
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* Pinmux_ops handling
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*/
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static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->nfuncs;
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}
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static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
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unsigned int selector)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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return info->funcs[selector].name;
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}
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static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
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unsigned int selector,
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const char * const **groups,
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unsigned int * const num_groups)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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*groups = info->funcs[selector].groups;
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*num_groups = info->funcs[selector].ngroups;
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return 0;
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}
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static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
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const char *name,
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struct armada_37xx_pin_group *grp)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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unsigned int reg = SELECTION;
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unsigned int mask = grp->reg_mask;
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int func, val;
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dev_dbg(info->dev, "enable function %s group %s\n",
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name, grp->name);
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func = match_string(grp->funcs, NB_FUNCS, name);
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if (func < 0)
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return -ENOTSUPP;
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val = grp->val[func];
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regmap_update_bits(info->regmap, reg, mask, val);
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return 0;
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}
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static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
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unsigned int selector,
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unsigned int group)
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{
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struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct armada_37xx_pin_group *grp = &info->groups[group];
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const char *name = info->funcs[selector].name;
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return armada_37xx_pmx_set_by_name(pctldev, name, grp);
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}
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static inline void armada_37xx_irq_update_reg(unsigned int *reg,
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struct irq_data *d)
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{
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int offset = irqd_to_hwirq(d);
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armada_37xx_update_reg(reg, &offset);
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}
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static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
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unsigned int reg = OUTPUT_EN;
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unsigned int mask;
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armada_37xx_update_reg(®, &offset);
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mask = BIT(offset);
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return regmap_update_bits(info->regmap, reg, mask, 0);
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}
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static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
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unsigned int reg = OUTPUT_EN;
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unsigned int val, mask;
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armada_37xx_update_reg(®, &offset);
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mask = BIT(offset);
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regmap_read(info->regmap, reg, &val);
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return !(val & mask);
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}
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static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
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unsigned int reg = OUTPUT_EN;
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unsigned int mask, val, ret;
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armada_37xx_update_reg(®, &offset);
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mask = BIT(offset);
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ret = regmap_update_bits(info->regmap, reg, mask, mask);
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if (ret)
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return ret;
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reg = OUTPUT_VAL;
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val = value ? mask : 0;
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regmap_update_bits(info->regmap, reg, mask, val);
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return 0;
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}
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static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
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unsigned int reg = INPUT_VAL;
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unsigned int val, mask;
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armada_37xx_update_reg(®, &offset);
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mask = BIT(offset);
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regmap_read(info->regmap, reg, &val);
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return (val & mask) != 0;
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}
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static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
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unsigned int reg = OUTPUT_VAL;
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unsigned int mask, val;
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armada_37xx_update_reg(®, &offset);
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mask = BIT(offset);
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val = value ? mask : 0;
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regmap_update_bits(info->regmap, reg, mask, val);
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}
|
|
|
|
static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int offset, bool input)
|
|
{
|
|
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
struct gpio_chip *chip = range->gc;
|
|
|
|
dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
|
|
offset, range->name, offset, input ? "input" : "output");
|
|
|
|
if (input)
|
|
armada_37xx_gpio_direction_input(chip, offset);
|
|
else
|
|
armada_37xx_gpio_direction_output(chip, offset, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int offset)
|
|
{
|
|
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
struct armada_37xx_pin_group *group;
|
|
int grp = 0;
|
|
|
|
dev_dbg(info->dev, "requesting gpio %d\n", offset);
|
|
|
|
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
|
|
armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinmux_ops armada_37xx_pmx_ops = {
|
|
.get_functions_count = armada_37xx_pmx_get_funcs_count,
|
|
.get_function_name = armada_37xx_pmx_get_func_name,
|
|
.get_function_groups = armada_37xx_pmx_get_groups,
|
|
.set_mux = armada_37xx_pmx_set,
|
|
.gpio_request_enable = armada_37xx_gpio_request_enable,
|
|
.gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
|
|
};
|
|
|
|
static const struct gpio_chip armada_37xx_gpiolib_chip = {
|
|
.request = gpiochip_generic_request,
|
|
.free = gpiochip_generic_free,
|
|
.set = armada_37xx_gpio_set,
|
|
.get = armada_37xx_gpio_get,
|
|
.get_direction = armada_37xx_gpio_get_direction,
|
|
.direction_input = armada_37xx_gpio_direction_input,
|
|
.direction_output = armada_37xx_gpio_direction_output,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static void armada_37xx_irq_ack(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
|
u32 reg = IRQ_STATUS;
|
|
unsigned long flags;
|
|
|
|
armada_37xx_irq_update_reg(®, d);
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
writel(d->mask, info->base + reg);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
}
|
|
|
|
static void armada_37xx_irq_mask(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
|
u32 val, reg = IRQ_EN;
|
|
unsigned long flags;
|
|
|
|
armada_37xx_irq_update_reg(®, d);
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
val = readl(info->base + reg);
|
|
writel(val & ~d->mask, info->base + reg);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
}
|
|
|
|
static void armada_37xx_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
|
u32 val, reg = IRQ_EN;
|
|
unsigned long flags;
|
|
|
|
armada_37xx_irq_update_reg(®, d);
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
val = readl(info->base + reg);
|
|
writel(val | d->mask, info->base + reg);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
}
|
|
|
|
static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
|
u32 val, reg = IRQ_WKUP;
|
|
unsigned long flags;
|
|
|
|
armada_37xx_irq_update_reg(®, d);
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
val = readl(info->base + reg);
|
|
if (on)
|
|
val |= (BIT(d->hwirq % GPIO_PER_REG));
|
|
else
|
|
val &= ~(BIT(d->hwirq % GPIO_PER_REG));
|
|
writel(val, info->base + reg);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
|
u32 val, reg = IRQ_POL;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
armada_37xx_irq_update_reg(®, d);
|
|
val = readl(info->base + reg);
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
val &= ~(BIT(d->hwirq % GPIO_PER_REG));
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
val |= (BIT(d->hwirq % GPIO_PER_REG));
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH: {
|
|
u32 in_val, in_reg = INPUT_VAL;
|
|
|
|
armada_37xx_irq_update_reg(&in_reg, d);
|
|
regmap_read(info->regmap, in_reg, &in_val);
|
|
|
|
/* Set initial polarity based on current input level. */
|
|
if (in_val & BIT(d->hwirq % GPIO_PER_REG))
|
|
val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
|
|
else
|
|
val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
|
|
break;
|
|
}
|
|
default:
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
return -EINVAL;
|
|
}
|
|
writel(val, info->base + reg);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
|
|
u32 pin_idx)
|
|
{
|
|
u32 reg_idx = pin_idx / GPIO_PER_REG;
|
|
u32 bit_num = pin_idx % GPIO_PER_REG;
|
|
u32 p, l, ret;
|
|
unsigned long flags;
|
|
|
|
regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
|
|
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
p = readl(info->base + IRQ_POL + 4 * reg_idx);
|
|
if ((p ^ l) & (1 << bit_num)) {
|
|
/*
|
|
* For the gpios which are used for both-edge irqs, when their
|
|
* interrupts happen, their input levels are changed,
|
|
* yet their interrupt polarities are kept in old values, we
|
|
* should synchronize their interrupt polarities; for example,
|
|
* at first a gpio's input level is low and its interrupt
|
|
* polarity control is "Detect rising edge", then the gpio has
|
|
* a interrupt , its level turns to high, we should change its
|
|
* polarity control to "Detect falling edge" correspondingly.
|
|
*/
|
|
p ^= 1 << bit_num;
|
|
writel(p, info->base + IRQ_POL + 4 * reg_idx);
|
|
ret = 0;
|
|
} else {
|
|
/* Spurious irq */
|
|
ret = -1;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static void armada_37xx_irq_handler(struct irq_desc *desc)
|
|
{
|
|
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
|
|
struct irq_domain *d = gc->irq.domain;
|
|
int i;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
|
|
u32 status;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
|
|
/* Manage only the interrupt that was enabled */
|
|
status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
while (status) {
|
|
u32 hwirq = ffs(status) - 1;
|
|
u32 virq = irq_find_mapping(d, hwirq +
|
|
i * GPIO_PER_REG);
|
|
u32 t = irq_get_trigger_type(virq);
|
|
|
|
if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
|
/* Swap polarity (race with GPIO line) */
|
|
if (armada_37xx_edge_both_irq_swap_pol(info,
|
|
hwirq + i * GPIO_PER_REG)) {
|
|
/*
|
|
* For spurious irq, which gpio level
|
|
* is not as expected after incoming
|
|
* edge, just ack the gpio irq.
|
|
*/
|
|
writel(1 << hwirq,
|
|
info->base +
|
|
IRQ_STATUS + 4 * i);
|
|
goto update_status;
|
|
}
|
|
}
|
|
|
|
generic_handle_irq(virq);
|
|
|
|
update_status:
|
|
/* Update status in case a new IRQ appears */
|
|
spin_lock_irqsave(&info->irq_lock, flags);
|
|
status = readl_relaxed(info->base +
|
|
IRQ_STATUS + 4 * i);
|
|
/* Manage only the interrupt that was enabled */
|
|
status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
|
|
spin_unlock_irqrestore(&info->irq_lock, flags);
|
|
}
|
|
}
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static unsigned int armada_37xx_irq_startup(struct irq_data *d)
|
|
{
|
|
/*
|
|
* The mask field is a "precomputed bitmask for accessing the
|
|
* chip registers" which was introduced for the generic
|
|
* irqchip framework. As we don't use this framework, we can
|
|
* reuse this field for our own usage.
|
|
*/
|
|
d->mask = BIT(d->hwirq % GPIO_PER_REG);
|
|
|
|
armada_37xx_irq_unmask(d);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
|
struct armada_37xx_pinctrl *info)
|
|
{
|
|
struct device_node *np = info->dev->of_node;
|
|
struct gpio_chip *gc = &info->gpio_chip;
|
|
struct irq_chip *irqchip = &info->irq_chip;
|
|
struct gpio_irq_chip *girq = &gc->irq;
|
|
struct device *dev = &pdev->dev;
|
|
struct resource res;
|
|
int ret = -ENODEV, i, nr_irq_parent;
|
|
|
|
/* Check if we have at least one gpio-controller child node */
|
|
for_each_child_of_node(info->dev->of_node, np) {
|
|
if (of_property_read_bool(np, "gpio-controller")) {
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (ret) {
|
|
dev_err(dev, "no gpio-controller child node\n");
|
|
return ret;
|
|
}
|
|
|
|
nr_irq_parent = platform_irq_count(pdev);
|
|
if (nr_irq_parent < 0) {
|
|
if (nr_irq_parent != -EPROBE_DEFER)
|
|
dev_err(dev, "Couldn't determine irq count: %pe\n",
|
|
ERR_PTR(nr_irq_parent));
|
|
return nr_irq_parent;
|
|
}
|
|
|
|
spin_lock_init(&info->irq_lock);
|
|
|
|
if (!nr_irq_parent) {
|
|
dev_err(dev, "invalid or no IRQ\n");
|
|
return 0;
|
|
}
|
|
|
|
if (of_address_to_resource(info->dev->of_node, 1, &res)) {
|
|
dev_err(dev, "cannot find IO resource\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
info->base = devm_ioremap_resource(info->dev, &res);
|
|
if (IS_ERR(info->base))
|
|
return PTR_ERR(info->base);
|
|
|
|
irqchip->irq_ack = armada_37xx_irq_ack;
|
|
irqchip->irq_mask = armada_37xx_irq_mask;
|
|
irqchip->irq_unmask = armada_37xx_irq_unmask;
|
|
irqchip->irq_set_wake = armada_37xx_irq_set_wake;
|
|
irqchip->irq_set_type = armada_37xx_irq_set_type;
|
|
irqchip->irq_startup = armada_37xx_irq_startup;
|
|
irqchip->name = info->data->name;
|
|
girq->chip = irqchip;
|
|
girq->parent_handler = armada_37xx_irq_handler;
|
|
/*
|
|
* Many interrupts are connected to the parent interrupt
|
|
* controller. But we do not take advantage of this and use
|
|
* the chained irq with all of them.
|
|
*/
|
|
girq->num_parents = nr_irq_parent;
|
|
girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
|
|
sizeof(*girq->parents), GFP_KERNEL);
|
|
if (!girq->parents)
|
|
return -ENOMEM;
|
|
for (i = 0; i < nr_irq_parent; i++) {
|
|
int irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0)
|
|
continue;
|
|
girq->parents[i] = irq;
|
|
}
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_edge_irq;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_gpiochip_register(struct platform_device *pdev,
|
|
struct armada_37xx_pinctrl *info)
|
|
{
|
|
struct device_node *np;
|
|
struct gpio_chip *gc;
|
|
int ret = -ENODEV;
|
|
|
|
for_each_child_of_node(info->dev->of_node, np) {
|
|
if (of_find_property(np, "gpio-controller", NULL)) {
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (ret)
|
|
return ret;
|
|
|
|
info->gpio_chip = armada_37xx_gpiolib_chip;
|
|
|
|
gc = &info->gpio_chip;
|
|
gc->ngpio = info->data->nr_pins;
|
|
gc->parent = &pdev->dev;
|
|
gc->base = -1;
|
|
gc->of_node = np;
|
|
gc->label = info->data->name;
|
|
|
|
ret = armada_37xx_irqchip_register(pdev, info);
|
|
if (ret)
|
|
return ret;
|
|
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* armada_37xx_add_function() - Add a new function to the list
|
|
* @funcs: array of function to add the new one
|
|
* @funcsize: size of the remaining space for the function
|
|
* @name: name of the function to add
|
|
*
|
|
* If it is a new function then create it by adding its name else
|
|
* increment the number of group associated to this function.
|
|
*/
|
|
static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
|
|
int *funcsize, const char *name)
|
|
{
|
|
int i = 0;
|
|
|
|
if (*funcsize <= 0)
|
|
return -EOVERFLOW;
|
|
|
|
while (funcs->ngroups) {
|
|
/* function already there */
|
|
if (strcmp(funcs->name, name) == 0) {
|
|
funcs->ngroups++;
|
|
|
|
return -EEXIST;
|
|
}
|
|
funcs++;
|
|
i++;
|
|
}
|
|
|
|
/* append new unique function */
|
|
funcs->name = name;
|
|
funcs->ngroups = 1;
|
|
(*funcsize)--;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* armada_37xx_fill_group() - complete the group array
|
|
* @info: info driver instance
|
|
*
|
|
* Based on the data available from the armada_37xx_pin_group array
|
|
* completes the last member of the struct for each function: the list
|
|
* of the groups associated to this function.
|
|
*
|
|
*/
|
|
static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
|
{
|
|
int n, num = 0, funcsize = info->data->nr_pins;
|
|
|
|
for (n = 0; n < info->ngroups; n++) {
|
|
struct armada_37xx_pin_group *grp = &info->groups[n];
|
|
int i, j, f;
|
|
|
|
grp->pins = devm_kcalloc(info->dev,
|
|
grp->npins + grp->extra_npins,
|
|
sizeof(*grp->pins),
|
|
GFP_KERNEL);
|
|
if (!grp->pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < grp->npins; i++)
|
|
grp->pins[i] = grp->start_pin + i;
|
|
|
|
for (j = 0; j < grp->extra_npins; j++)
|
|
grp->pins[i+j] = grp->extra_pin + j;
|
|
|
|
for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
|
|
int ret;
|
|
/* check for unique functions and count groups */
|
|
ret = armada_37xx_add_function(info->funcs, &funcsize,
|
|
grp->funcs[f]);
|
|
if (ret == -EOVERFLOW)
|
|
dev_err(info->dev,
|
|
"More functions than pins(%d)\n",
|
|
info->data->nr_pins);
|
|
if (ret < 0)
|
|
continue;
|
|
num++;
|
|
}
|
|
}
|
|
|
|
info->nfuncs = num;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* armada_37xx_fill_funcs() - complete the funcs array
|
|
* @info: info driver instance
|
|
*
|
|
* Based on the data available from the armada_37xx_pin_group array
|
|
* completes the last two member of the struct for each group:
|
|
* - the list of the pins included in the group
|
|
* - the list of pinmux functions that can be selected for this group
|
|
*
|
|
*/
|
|
static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
|
|
{
|
|
struct armada_37xx_pmx_func *funcs = info->funcs;
|
|
int n;
|
|
|
|
for (n = 0; n < info->nfuncs; n++) {
|
|
const char *name = funcs[n].name;
|
|
const char **groups;
|
|
int g;
|
|
|
|
funcs[n].groups = devm_kcalloc(info->dev,
|
|
funcs[n].ngroups,
|
|
sizeof(*(funcs[n].groups)),
|
|
GFP_KERNEL);
|
|
if (!funcs[n].groups)
|
|
return -ENOMEM;
|
|
|
|
groups = funcs[n].groups;
|
|
|
|
for (g = 0; g < info->ngroups; g++) {
|
|
struct armada_37xx_pin_group *gp = &info->groups[g];
|
|
int f;
|
|
|
|
f = match_string(gp->funcs, NB_FUNCS, name);
|
|
if (f < 0)
|
|
continue;
|
|
|
|
*groups = gp->name;
|
|
groups++;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int armada_37xx_pinctrl_register(struct platform_device *pdev,
|
|
struct armada_37xx_pinctrl *info)
|
|
{
|
|
const struct armada_37xx_pin_data *pin_data = info->data;
|
|
struct pinctrl_desc *ctrldesc = &info->pctl;
|
|
struct pinctrl_pin_desc *pindesc, *pdesc;
|
|
int pin, ret;
|
|
|
|
info->groups = pin_data->groups;
|
|
info->ngroups = pin_data->ngroups;
|
|
|
|
ctrldesc->name = "armada_37xx-pinctrl";
|
|
ctrldesc->owner = THIS_MODULE;
|
|
ctrldesc->pctlops = &armada_37xx_pctrl_ops;
|
|
ctrldesc->pmxops = &armada_37xx_pmx_ops;
|
|
ctrldesc->confops = &armada_37xx_pinconf_ops;
|
|
|
|
pindesc = devm_kcalloc(&pdev->dev,
|
|
pin_data->nr_pins, sizeof(*pindesc),
|
|
GFP_KERNEL);
|
|
if (!pindesc)
|
|
return -ENOMEM;
|
|
|
|
ctrldesc->pins = pindesc;
|
|
ctrldesc->npins = pin_data->nr_pins;
|
|
|
|
pdesc = pindesc;
|
|
for (pin = 0; pin < pin_data->nr_pins; pin++) {
|
|
pdesc->number = pin;
|
|
pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
|
|
pin_data->name, pin);
|
|
pdesc++;
|
|
}
|
|
|
|
/*
|
|
* we allocate functions for number of pins and hope there are
|
|
* fewer unique functions than pins available
|
|
*/
|
|
info->funcs = devm_kcalloc(&pdev->dev,
|
|
pin_data->nr_pins,
|
|
sizeof(struct armada_37xx_pmx_func),
|
|
GFP_KERNEL);
|
|
if (!info->funcs)
|
|
return -ENOMEM;
|
|
|
|
|
|
ret = armada_37xx_fill_group(info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = armada_37xx_fill_func(info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
|
|
if (IS_ERR(info->pctl_dev)) {
|
|
dev_err(&pdev->dev, "could not register pinctrl driver\n");
|
|
return PTR_ERR(info->pctl_dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PM)
|
|
static int armada_3700_pinctrl_suspend(struct device *dev)
|
|
{
|
|
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
|
|
|
|
/* Save GPIO state */
|
|
regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
|
|
regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
|
|
regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
|
|
regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
|
|
&info->pm.out_val_h);
|
|
|
|
info->pm.irq_en_l = readl(info->base + IRQ_EN);
|
|
info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
|
|
info->pm.irq_pol_l = readl(info->base + IRQ_POL);
|
|
info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
|
|
|
|
/* Save pinctrl state */
|
|
regmap_read(info->regmap, SELECTION, &info->pm.selection);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armada_3700_pinctrl_resume(struct device *dev)
|
|
{
|
|
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
|
|
struct gpio_chip *gc;
|
|
struct irq_domain *d;
|
|
int i;
|
|
|
|
/* Restore GPIO state */
|
|
regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
|
|
regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
|
|
info->pm.out_en_h);
|
|
regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
|
|
regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
|
|
info->pm.out_val_h);
|
|
|
|
/*
|
|
* Input levels may change during suspend, which is not monitored at
|
|
* that time. GPIOs used for both-edge IRQs may not be synchronized
|
|
* anymore with their polarities (rising/falling edge) and must be
|
|
* re-configured manually.
|
|
*/
|
|
gc = &info->gpio_chip;
|
|
d = gc->irq.domain;
|
|
for (i = 0; i < gc->ngpio; i++) {
|
|
u32 irq_bit = BIT(i % GPIO_PER_REG);
|
|
u32 mask, *irq_pol, input_reg, virq, type, level;
|
|
|
|
if (i < GPIO_PER_REG) {
|
|
mask = info->pm.irq_en_l;
|
|
irq_pol = &info->pm.irq_pol_l;
|
|
input_reg = INPUT_VAL;
|
|
} else {
|
|
mask = info->pm.irq_en_h;
|
|
irq_pol = &info->pm.irq_pol_h;
|
|
input_reg = INPUT_VAL + sizeof(u32);
|
|
}
|
|
|
|
if (!(mask & irq_bit))
|
|
continue;
|
|
|
|
virq = irq_find_mapping(d, i);
|
|
type = irq_get_trigger_type(virq);
|
|
|
|
/*
|
|
* Synchronize level and polarity for both-edge irqs:
|
|
* - a high input level expects a falling edge,
|
|
* - a low input level exepects a rising edge.
|
|
*/
|
|
if ((type & IRQ_TYPE_SENSE_MASK) ==
|
|
IRQ_TYPE_EDGE_BOTH) {
|
|
regmap_read(info->regmap, input_reg, &level);
|
|
if ((*irq_pol ^ level) & irq_bit)
|
|
*irq_pol ^= irq_bit;
|
|
}
|
|
}
|
|
|
|
writel(info->pm.irq_en_l, info->base + IRQ_EN);
|
|
writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
|
|
writel(info->pm.irq_pol_l, info->base + IRQ_POL);
|
|
writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
|
|
|
|
/* Restore pinctrl state */
|
|
regmap_write(info->regmap, SELECTION, info->pm.selection);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Since pinctrl is an infrastructure module, its resume should be issued prior
|
|
* to other IO drivers.
|
|
*/
|
|
static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
|
|
.suspend_noirq = armada_3700_pinctrl_suspend,
|
|
.resume_noirq = armada_3700_pinctrl_resume,
|
|
};
|
|
|
|
#define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
|
|
#else
|
|
#define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
|
|
{
|
|
.compatible = "marvell,armada3710-sb-pinctrl",
|
|
.data = &armada_37xx_pin_sb,
|
|
},
|
|
{
|
|
.compatible = "marvell,armada3710-nb-pinctrl",
|
|
.data = &armada_37xx_pin_nb,
|
|
},
|
|
{ },
|
|
};
|
|
|
|
static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct armada_37xx_pinctrl *info;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
|
|
GFP_KERNEL);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
info->dev = dev;
|
|
|
|
regmap = syscon_node_to_regmap(np);
|
|
if (IS_ERR(regmap)) {
|
|
dev_err(&pdev->dev, "cannot get regmap\n");
|
|
return PTR_ERR(regmap);
|
|
}
|
|
info->regmap = regmap;
|
|
|
|
info->data = of_device_get_match_data(dev);
|
|
|
|
ret = armada_37xx_pinctrl_register(pdev, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = armada_37xx_gpiochip_register(pdev, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver armada_37xx_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "armada-37xx-pinctrl",
|
|
.of_match_table = armada_37xx_pinctrl_of_match,
|
|
.pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
|
|
armada_37xx_pinctrl_probe);
|