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ca6b5fe277
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230310144715.1543836-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
371 lines
10 KiB
C
371 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Marvell International Ltd.
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* Zhangfei Gao <zhangfei.gao@marvell.com>
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* Kevin Wang <dwang4@marvell.com>
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* Jun Nie <njun@marvell.com>
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* Qiming Wu <wuqm@marvell.com>
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* Philip Rakity <prakity@marvell.com>
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <linux/platform_data/pxa_sdhci.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/pinctrl/consumer.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#define SD_FIFO_PARAM 0xe0
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#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
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#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
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#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
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#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
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CLK_GATE_ON | CLK_GATE_CTL)
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#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
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#define SDCLK_SEL_SHIFT 8
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#define SDCLK_SEL_MASK 0x3
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#define SDCLK_DELAY_SHIFT 10
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#define SDCLK_DELAY_MASK 0x3c
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#define SD_CE_ATA_2 0xea
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#define MMC_CARD 0x1000
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#define MMC_WIDTH 0x0100
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struct sdhci_pxav2_host {
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struct mmc_request *sdio_mrq;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_cmd_gpio;
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};
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static void pxav2_reset(struct sdhci_host *host, u8 mask)
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{
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struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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sdhci_reset(host, mask);
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if (mask == SDHCI_RESET_ALL) {
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u16 tmp = 0;
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/*
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* tune timing of read data/command when crc error happen
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* no performance impact
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*/
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if (pdata && pdata->clk_delay_sel == 1) {
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tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
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tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
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<< SDCLK_DELAY_SHIFT;
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tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
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tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
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writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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}
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if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
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tmp = readw(host->ioaddr + SD_FIFO_PARAM);
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tmp &= ~CLK_GATE_SETTING_BITS;
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writew(tmp, host->ioaddr + SD_FIFO_PARAM);
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} else {
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tmp = readw(host->ioaddr + SD_FIFO_PARAM);
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tmp &= ~CLK_GATE_SETTING_BITS;
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tmp |= CLK_GATE_SETTING_BITS;
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writew(tmp, host->ioaddr + SD_FIFO_PARAM);
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}
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}
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}
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static u16 pxav1_readw(struct sdhci_host *host, int reg)
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{
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/* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */
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if (reg == SDHCI_HOST_VERSION)
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return readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16;
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return readw(host->ioaddr + reg);
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}
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static u32 pxav1_irq(struct sdhci_host *host, u32 intmask)
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{
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struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(sdhci_priv(host));
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struct mmc_request *sdio_mrq;
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if (pxav2_host->sdio_mrq && (intmask & SDHCI_INT_CMD_MASK)) {
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/* The dummy CMD0 for the SDIO workaround just completed */
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sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS);
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intmask &= ~SDHCI_INT_CMD_MASK;
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/* Restore MMC function to CMD pin */
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if (pxav2_host->pinctrl && pxav2_host->pins_default)
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pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default);
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sdio_mrq = pxav2_host->sdio_mrq;
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pxav2_host->sdio_mrq = NULL;
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mmc_request_done(host->mmc, sdio_mrq);
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}
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return intmask;
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}
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static void pxav1_request_done(struct sdhci_host *host, struct mmc_request *mrq)
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{
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u16 tmp;
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struct sdhci_pxav2_host *pxav2_host;
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/* If this is an SDIO command, perform errata workaround for silicon bug */
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if (mrq->cmd && !mrq->cmd->error &&
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(mrq->cmd->opcode == SD_IO_RW_DIRECT ||
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mrq->cmd->opcode == SD_IO_RW_EXTENDED)) {
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/* Reset data port */
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tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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tmp |= 0x400;
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writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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/* Clock is now stopped, so restart it by sending a dummy CMD0 */
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pxav2_host = sdhci_pltfm_priv(sdhci_priv(host));
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pxav2_host->sdio_mrq = mrq;
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/* Set CMD as high output rather than MMC function while we do CMD0 */
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if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio)
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pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio);
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sdhci_writel(host, 0, SDHCI_ARGUMENT);
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sdhci_writew(host, 0, SDHCI_TRANSFER_MODE);
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sdhci_writew(host, SDHCI_MAKE_CMD(MMC_GO_IDLE_STATE, SDHCI_CMD_RESP_NONE),
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SDHCI_COMMAND);
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/* Don't finish this request until the dummy CMD0 finishes */
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return;
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}
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mmc_request_done(host->mmc, mrq);
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}
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static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
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{
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u8 ctrl;
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u16 tmp;
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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if (width == MMC_BUS_WIDTH_8) {
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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tmp |= MMC_CARD | MMC_WIDTH;
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} else {
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tmp &= ~(MMC_CARD | MMC_WIDTH);
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if (width == MMC_BUS_WIDTH_4)
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ctrl |= SDHCI_CTRL_4BITBUS;
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else
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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}
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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struct sdhci_pxa_variant {
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const struct sdhci_ops *ops;
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unsigned int extra_quirks;
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};
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static const struct sdhci_ops pxav1_sdhci_ops = {
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.read_w = pxav1_readw,
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.set_clock = sdhci_set_clock,
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.irq = pxav1_irq,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = pxav2_mmc_set_bus_width,
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.reset = pxav2_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.request_done = pxav1_request_done,
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};
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static const struct sdhci_pxa_variant __maybe_unused pxav1_variant = {
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.ops = &pxav1_sdhci_ops,
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.extra_quirks = SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE,
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};
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static const struct sdhci_ops pxav2_sdhci_ops = {
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = pxav2_mmc_set_bus_width,
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.reset = pxav2_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pxa_variant pxav2_variant = {
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.ops = &pxav2_sdhci_ops,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id sdhci_pxav2_of_match[] = {
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{ .compatible = "mrvl,pxav1-mmc", .data = &pxav1_variant, },
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{ .compatible = "mrvl,pxav2-mmc", .data = &pxav2_variant, },
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
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static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
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{
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struct sdhci_pxa_platdata *pdata;
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struct device_node *np = dev->of_node;
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u32 bus_width;
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u32 clk_delay_cycles;
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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if (of_property_read_bool(np, "non-removable"))
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pdata->flags |= PXA_FLAG_CARD_PERMANENT;
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of_property_read_u32(np, "bus-width", &bus_width);
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if (bus_width == 8)
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pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
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of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
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if (clk_delay_cycles > 0) {
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pdata->clk_delay_sel = 1;
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pdata->clk_delay_cycles = clk_delay_cycles;
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}
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return pdata;
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}
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#else
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static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
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{
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return NULL;
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}
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#endif
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static int sdhci_pxav2_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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struct sdhci_pxav2_host *pxav2_host;
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struct device *dev = &pdev->dev;
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struct sdhci_host *host = NULL;
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const struct sdhci_pxa_variant *variant;
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int ret;
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struct clk *clk, *clk_core;
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host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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pxav2_host = sdhci_pltfm_priv(pltfm_host);
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clk = devm_clk_get(dev, "io");
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if (IS_ERR(clk) && PTR_ERR(clk) != -EPROBE_DEFER)
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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dev_err_probe(dev, ret, "failed to get io clock\n");
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goto free;
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}
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pltfm_host->clk = clk;
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "failed to enable io clock\n");
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goto free;
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}
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clk_core = devm_clk_get_optional_enabled(dev, "core");
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if (IS_ERR(clk_core)) {
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ret = PTR_ERR(clk_core);
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dev_err_probe(dev, ret, "failed to enable core clock\n");
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goto disable_clk;
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}
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host->quirks = SDHCI_QUIRK_BROKEN_ADMA
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| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
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| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
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variant = of_device_get_match_data(dev);
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if (variant)
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pdata = pxav2_get_mmc_pdata(dev);
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else
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variant = &pxav2_variant;
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if (pdata) {
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if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
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/* on-chip device */
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host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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}
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/* If slot design supports 8 bit data, indicate this to MMC. */
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if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
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host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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if (pdata->quirks)
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host->quirks |= pdata->quirks;
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if (pdata->host_caps)
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host->mmc->caps |= pdata->host_caps;
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if (pdata->pm_caps)
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host->mmc->pm_caps |= pdata->pm_caps;
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}
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host->quirks |= variant->extra_quirks;
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host->ops = variant->ops;
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/* Set up optional pinctrl for PXA168 SDIO IRQ fix */
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pxav2_host->pinctrl = devm_pinctrl_get(dev);
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if (!IS_ERR(pxav2_host->pinctrl)) {
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pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl,
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"state_cmd_gpio");
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if (IS_ERR(pxav2_host->pins_cmd_gpio))
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pxav2_host->pins_cmd_gpio = NULL;
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pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl,
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"default");
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if (IS_ERR(pxav2_host->pins_default))
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pxav2_host->pins_default = NULL;
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} else {
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pxav2_host->pinctrl = NULL;
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}
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ret = sdhci_add_host(host);
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if (ret)
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goto disable_clk;
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return 0;
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disable_clk:
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clk_disable_unprepare(clk);
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free:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static struct platform_driver sdhci_pxav2_driver = {
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.driver = {
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.name = "sdhci-pxav2",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = of_match_ptr(sdhci_pxav2_of_match),
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.pm = &sdhci_pltfm_pmops,
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},
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.probe = sdhci_pxav2_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_pxav2_driver);
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MODULE_DESCRIPTION("SDHCI driver for pxav2");
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MODULE_AUTHOR("Marvell International Ltd.");
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MODULE_LICENSE("GPL v2");
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